initial commit
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parent
26be535f5d
commit
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import sys
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ap_count = 0
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file_write = ["module Prop where\nimport Clash.Prelude\nimport ProcessingElement(processingElement)\nimport Queue(queue,queuetest)\nimport Queue30(queue30,queuetest30)\n\n"]
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tt_temp = {'!':["not","(1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31))"],
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'G':["box","(1,(31,31,31,31,0,0,t2,t2,31,31),(31,31,t1,t2,0,0,31,31,31,31))"],
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'F':["diamond","(1,(t1,t2,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,t2,t2))"],
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'H':["box","(1,(31,31,31,31,0,0,t2,t2,31,31),(31,31,0,t2,0,0,31,31,31,31))"],
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'E':["diamond","(1,(0,t2,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,t2,t2))"],
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'X':["next","(1,(1,1,31,31,0,0,31,31,31,31),(31,31,1,1,0,0,31,31,31,31))"],
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'v':["or","(0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31))"],
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'U':["(1,(31,31,31,31,0,0,31,31,31,31),(31,31,0,t1-1,31,31,31,31,31,31))",
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"(1,(31,31,31,31,31,31,t1,t2,31,31),(31,31,31,31,31,31,31,31,t2,t2))",
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"(0,(31,31,31,31,31,31,31,31,31,31),(31,31,31,31,31,31,31,31,t1,t2))"]}
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class node:
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def __init__(self,val,left=None,right=None,t1=0,t2=0,isbinary=0,isunary=0,isap=0,q_no=0,q_mealy="",pe_mealy=""):
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self.val=val
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self.left=left
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self.right=right
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self.t1 = t1
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self.t2 = t2
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self.isbinary = isbinary
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self.isunary = isunary
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self.isap = isap
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self.q_no = q_no
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self.q_mealy = q_mealy
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self.pe_mealy = pe_mealy
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def precedence(op):
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if op == '!':
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return 11
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elif op == 'G':
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return 10
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elif op == 'H':
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return 9
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elif op == 'F':
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return 8
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elif op == 'E':
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return 7
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elif op == 'X':
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return 6
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elif op == 'U':
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return 5
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elif op == '^':
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return 4
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elif op == 'v':
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return 3
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elif op == '>':
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return 2
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else:
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return 1
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root = [node('')]
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def construc_tree(r,expr):
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cur = r
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parent = []
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i = 0
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while i < len(expr):
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if expr[i] in ['E','H','X','!','G','F']:
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cur.isunary = 1
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if expr[i] in ['E','H']:
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cur.t1 = 0
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cur.t2 = int(expr[i+1])
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elif expr[i] in ['G','F']:
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temp = expr[i:-1].index(']')+i
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cur.t1, cur.t2 = map(int , expr[i+2:temp].split(','))
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elif expr[i] in ['U','^','v','>']:
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cur.isbinary = 1
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if expr[i] in ['G','F','U']:
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temp = expr[i:-1].index(']')+i
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cur.t1, cur.t2 = map(int , expr[i+2:temp].split(','))
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if expr[i] in ['^','v','>','U','G','F','H','E','U','X','!']:
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# first check the precedence of the operator to his parent operator
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# if the precedence of the operator is less than the parent operator
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# then pop till the parent operator and make it the left child of the operator
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# if the parent is empty then make the operator as the root
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# if the parent is not empty then make the operator as the right child of the parent
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# and make the parent as the parent of the operator
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# make the operator as the current node
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par = None
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ch = False
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while parent and (precedence(expr[i]) < precedence(parent[-1].val)):
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par = parent.pop()
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ch = True
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if ch:
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new = node(expr[i])
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if parent:
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temp = parent[-1].right
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parent[-1].right = new
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new.left = temp
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else:
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new.left = root[0]
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root[0] = new
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parent.append(new)
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new.right = node('')
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cur = new.right
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else:
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cur.val = expr[i]
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cur.right = node('')
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parent.append(cur)
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cur = cur.right
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else:
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if expr[i].isalpha():
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cur.left = node(expr[i])
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cur.left.isap = 1
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i =i+ 1
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def manage_implies_and(root):
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if root != None and root != "":
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manage_implies_and(root.left)
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manage_implies_and(root.right)
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if root.val == '>':
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new = node('!')
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new.isunary = 1
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root.val = 'v'
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root.isbinary = 1
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new.left = root.left
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elif root.val == '^':
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new1 = node('!')
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new1.isunary = 1
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new2 = node('!')
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new2.isunary = 1
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new3 = node('v')
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new3.isbinary = 1
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root.val = '!'
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new1.left = root.left
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new2.left = root.right
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new3.left = new1
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new3.right = new2
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root.left = new3
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root.isbinary = 0
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root.isunary = 1
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root.right = None
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file = "property.txt"
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f = open(file, "r")
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data = f.readlines()
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ex = data[0][:-1]
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construc_tree(root[0],ex)
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manage_implies_and(root[0])
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Q_ID = 1
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def post_order(root):
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global Q_ID
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global ap_count
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if root != None:
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post_order(root.left)
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post_order(root.right)
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if root != None and root != "" and (not (root.isap == 0 and root.isbinary == 0 and root.isunary == 0)) and (root.val != ""):
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print("-" + root.val+"-")
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print(root.t1)
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print(root.t2)
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print(root.isap)
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print(root.isunary)
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print(root.isbinary)
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if root.isap == 0:
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t = '0:>Nil'
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t1 = ""
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for x in range(root.t2):
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t2 = "0:>"
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t1 = t1 + t2
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t = t1+t
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if root.val != 'U':
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print("queue_mealy_"+str(Q_ID)+" inp = mealy queue ("+t+") inp")
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file_write.append("queue_mealy_"+str(Q_ID)+" inp = mealy queue ("+t+") inp\n")
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elif root.val == 'U':
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print("queue_mealy_"+str(Q_ID)+" inp = mealy queue30 ("+t+") inp")
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file_write.append("queue_mealy_"+str(Q_ID)+" inp = mealy queue30 ("+t+") inp\n")
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root.q_mealy = "queue_mealy_"+str(Q_ID)
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root.q_no = Q_ID
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Q_ID+=1
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elif root.isap == 1:
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print('inp'+root.val)
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root.q_mealy = 'inp'+root.val
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ap_count+=1
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if root.val in ['H','E']:
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tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2))
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elif root.val in ['G','F']:
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tt_temp[root.val][1] = tt_temp[root.val][1].replace("t1",str(root.t1))
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tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2))
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elif root.val in ['U']:
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tt_temp[root.val][0] = tt_temp[root.val][0].replace("t1-1",str(root.t1-1))
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tt_temp[root.val][1] = tt_temp[root.val][1].replace("t1",str(root.t1))
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tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2))
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tt_temp[root.val][2] = tt_temp[root.val][2].replace("t1",str(root.t1))
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tt_temp[root.val][2] = tt_temp[root.val][2].replace("t2",str(root.t2))
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if root.isap == 0:
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if root.val != 'U':
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file_write.append("processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no)+" inp = mealy processingElement "+tt_temp[root.val][1] +" inp\n\n")
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print("processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no)+" inp = mealy processingElement "+tt_temp[root.val][1] +" inp\n")
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root.pe_mealy = "processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no)
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elif root.val == 'U':
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file_write.append("processingElement_mealy_until1"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][0]+" inp\n")
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file_write.append("processingElement_mealy_until2"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][1]+" inp\n")
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file_write.append("processingElement_mealy_until3"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][2]+" inp\n\n")
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file_write.append("until_out"+str(root.q_no)+" (inp1,inp2) = "+root.q_mealy+" (bundle (processingElement_mealy_until1"+str(root.q_no)+" (bundle ( inp1, inp1)), processingElement_mealy_until2"+str(root.q_no)+" (bundle ( inp2, inp2)), processingElement_mealy_until3"+str(root.q_no)+" (bundle ( inp1, inp2))))\n\n")
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print("processingElement_mealy_until1"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][0]+" inp")
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print("processingElement_mealy_until2"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][1]+" inp")
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print("processingElement_mealy_until3"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][2]+" inp\n")
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print("until_out"+str(root.q_no)+" (inp1,inp2) = "+root.q_mealy+" (bundle (processingElement_mealy_until1"+str(root.q_no)+" (bundle ( inp1, inp1)), processingElement_mealy_until2"+str(root.q_no)+" (bundle ( inp2, inp2)), processingElement_mealy_until3"+str(root.q_no)+" (bundle ( inp1, inp2))))\n")
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root.pe_mealy = "until_out"+str(root.q_no)
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elif root.isap == 1:
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print('inp'+root.val)
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root.pe_mealy = 'inp'+root.val
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print('\n')
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post_order(root[0])
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prop = ""
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def final_prop(root):
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if root != None and root != "" and (not (root.isap == 0 and root.isbinary == 0 and root.isunary == 0)) and (root.val != ""):
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if root.val != 'U':
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if root.isap == 1:
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return(root.pe_mealy)
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elif root.isunary == 1:
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if root.left != None:
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return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.left) + ") , (" + final_prop(root.left) + ") ) ) )")
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if root.right != None:
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return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.right) + ") , (" + final_prop(root.right) + ") ) ) )")
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elif root.isbinary == 1:
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return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.left) + ") , (" + final_prop(root.right) + ") ) ) )")
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elif root.val == 'U':
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return(root.pe_mealy+" ( "+"("+final_prop(root.left)+") , ("+final_prop(root.right)+") )")
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elif root != None and root.val == "":
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if root.left != None:
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return(final_prop(root.left))
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else:
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return(final_prop(root.right))
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else:
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return("")
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property = "prop ("
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def prop_lhs(root):
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global property
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if root != None and root != "":
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prop_lhs(root.left)
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prop_lhs(root.right)
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if root.isap == 1:
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property = property + "inp"+root.val+","
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prop_lhs(root[0])
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#https://stackoverflow.com/questions/423379/using-global-variables-in-a-function
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def replacer(s, newstring, index, nofail=False):
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# raise an error if index is outside of the string
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if not nofail and index not in range(len(s)):
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raise ValueError("index outside given string")
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# if not erroring, but the index is still not in the correct range..
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if index < 0: # add it to the beginning
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return newstring + s
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if index > len(s): # add it to the end
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return s + newstring
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# insert the new string between "slices" of the original
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return s[:index] + newstring + s[index + 1:]
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property = replacer(property,') = ',len(property)-1)
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property = property + final_prop(root[0]) + '\n\n'
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file_write.append(property)
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print(property)
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n_ips = ""
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for i in range(ap_count):
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if ap_count-1 == i:
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n_ips = n_ips + "Signal System (Bool)"
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else:
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n_ips = "Signal System (Bool)" + " , " + n_ips
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file_write.append("topEntity\n :: Clock System\n -> Reset System\n -> Enable System\n -> ("+n_ips+")\n -> Signal System ( Bool)\ntopEntity = exposeClockResetEnable prop\n\n")
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f = open("Prop.hs", "w")
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f.writelines(file_write)
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f.close()
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@ -0,0 +1,23 @@
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module ProcessingElement where
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import Clash.Explicit.Testbench
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import Clash.Prelude
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f (x,y) = x
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g (x,y) = y
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size=5
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processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size))
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processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where
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currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
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(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
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| ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t)
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| otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)
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--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
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--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
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-- 1 = True
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-- (-1) = False
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-- 0 = Maybe
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-- mealy functions have type: current_state -> input -> (new_state, output)
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@ -0,0 +1,25 @@
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module Prop where
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import Clash.Prelude
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import ProcessingElement(processingElement)
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import Queue(queue,queuetest)
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import Queue30(queue30,queuetest30)
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queue_mealy_1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
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processingElement_mealy_A inp = mealy processingElement (1,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
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queue_mealy_2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
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processingElement_mealy_box2 inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp
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queue_mealy_3 inp = mealy queue (0:>Nil) inp
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processingElement_mealy_or3 inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
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prop (inpA,inpB) = queue_mealy_3 ( processingElement_mealy_or3 ( bundle ( (( queue_mealy_1 ( processingElement_mealy_A ( bundle ( inpA , inpA )) ) )) , (queue_mealy_2 ( processingElement_mealy_box2 ( bundle ( (inpB) , (inpB) ) ) )) ) ) )
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topEntity
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:: Clock System
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-> Reset System
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-> Enable System
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-> (Signal System (Bool) , Signal System (Bool))
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-> Signal System ( Bool)
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topEntity = exposeClockResetEnable prop
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|
@ -0,0 +1,30 @@
|
|||
module Queue where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2))
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
module Queue30 where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
(tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23)
|
||||
|
||||
queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)))
|
||||
|
||||
queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
|
||||
--import qualified Data.List as L
|
||||
-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ]
|
||||
|
|
@ -0,0 +1 @@
|
|||
AvG[2,5]B
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module ProcessingElement where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
size=5
|
||||
processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size))
|
||||
processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where
|
||||
currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t)
|
||||
| otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)
|
||||
|
||||
--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
-- mealy functions have type: current_state -> input -> (new_state, output)
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
module Queue where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2))
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
module Queue30 where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
(tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23)
|
||||
|
||||
queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)))
|
||||
|
||||
queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
|
||||
--import qualified Data.List as L
|
||||
-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ]
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
module Operators where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
import ProcessingElement(processingElement)
|
||||
import Queue(queue,queuetest)
|
||||
import Queue30(queue30,queuetest30)
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
queue_mealy11 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
-- in until1 '1 --> t1-1'
|
||||
processingElement_mealy_until1 inp = mealy processingElement (1,(31,31,31,31,0,0,31,31,31,31),(31,31,0,1,31,31,31,31,31,31)) inp
|
||||
processingElement_mealy_until2 inp = mealy processingElement (1,(31,31,31,31,31,31,2,5,31,31),(31,31,31,31,31,31,31,31,5,5)) inp
|
||||
processingElement_mealy_until3 inp = mealy processingElement (0,(31,31,31,31,31,31,31,31,31,31),(31,31,31,31,31,31,31,31,2,5)) inp
|
||||
until_out (inp1,inp2) = queue_mealy11 (bundle (processingElement_mealy_until1 (bundle ( inp1, inp1)), processingElement_mealy_until2 (bundle ( inp2, inp2)), processingElement_mealy_until3 (bundle ( inp1, inp2))))
|
||||
|
||||
queue_mealy1 inp = mealy queue (0:>0:>0:>0:>1:>0:>Nil) inp
|
||||
queue_mealy2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
queue_mealy3 inp = mealy queue (0:>Nil) inp
|
||||
|
||||
processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
|
||||
or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1, inp2)))
|
||||
|
||||
processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
|
||||
not_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_not (bundle ( inp1, inp2)))
|
||||
|
||||
processingElement_mealy_box3 inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp
|
||||
box_out inp1 =queue_mealy2 (processingElement_mealy_box3 (bundle ( inp1, inp1)))
|
||||
|
||||
prop (inp1,inp2) = until_out (inp1 , (queue_mealy2 (processingElement_mealy_box3 (bundle (inp2,inp2)))))
|
||||
|
||||
processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp
|
||||
diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1, inp2)))
|
||||
|
||||
--topEntity
|
||||
-- :: Clock System
|
||||
-- -> Reset System
|
||||
-- -> Enable System
|
||||
-- -> (Signal System (Bool), Signal System (Bool))
|
||||
-- -> Signal System (Vec 6 (Signed 2), Bool)
|
||||
--topEntity = exposeClockResetEnable until_out
|
||||
|
||||
--testBench :: Signal System Bool
|
||||
--testBench = done
|
||||
-- where
|
||||
-- testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False])
|
||||
-- testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False])
|
||||
-- expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)])
|
||||
-- done = expectOutput (topEntity clk rst en (testInput1, testInput2))
|
||||
-- en = enableGen
|
||||
-- clk = tbSystemClockGen (not <$> done)
|
||||
-- rst = systemResetGen
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
module Operators where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
import ProcessingElement(processingElement)
|
||||
import Queue(queue,queuetest)
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
queue_mealy1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
queue_mealy2 inp = mealy queuetest (0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
queue_mealy3 inp = mealy queuetest (0:>Nil) inp
|
||||
|
||||
processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
|
||||
or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1, inp2)))
|
||||
|
||||
processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
|
||||
not_out inp1 =queue_mealy3 (processingElement_mealy_not (bundle ( inp1, inp1)))
|
||||
|
||||
processingElement_mealy_box inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp
|
||||
box_out inp1 =queue_mealy2 (processingElement_mealy_box (bundle ( inp1, inp1)))
|
||||
|
||||
processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp
|
||||
diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1, inp2)))
|
||||
|
||||
--topEntity
|
||||
-- :: Clock System
|
||||
-- -> Reset System
|
||||
-- -> Enable System
|
||||
-- -> (Signal System (Bool))
|
||||
-- -> Signal System (Vec 6 (Signed 2), Bool)
|
||||
--topEntity = exposeClockResetEnable box_out
|
||||
|
||||
--testBench :: Signal System Bool
|
||||
--testBench = done
|
||||
-- where
|
||||
-- testInput1 = stimuliGenerator clk rst $(listToVecTH [True::Bool , False, False, False, False, True, False, False, True, True, True, True, False])
|
||||
-- testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False])
|
||||
-- expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)])
|
||||
-- done = expectOutput (topEntity clk rst en (testInput1, testInput2))
|
||||
-- en = enableGen
|
||||
-- clk = tbSystemClockGen (not <$> done)
|
||||
-- rst = systemResetGen
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module ProcessingElement where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
size=5
|
||||
processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size))
|
||||
processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where
|
||||
currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t)
|
||||
| otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)
|
||||
|
||||
--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
-- mealy functions have type: current_state -> input -> (new_state, output)
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
module Queue where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2))
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
module Queue30 where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
(tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23)
|
||||
|
||||
queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)))
|
||||
|
||||
queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
|
||||
--import qualified Data.List as L
|
||||
-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ]
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
module Notofnot where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
import ProcessingElement(processingElement)
|
||||
import Queue(queue,queuetest)
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
queue_mealy1 inp = mealy queue (0:>Nil) inp
|
||||
--size=5
|
||||
--queue_mealy2 :: HiddenClockResetEnable dom => Signal dom (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> Signal dom Bool
|
||||
queue_mealy2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
processingElement_mealy_not1 inp = mealy processingElement (0,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
|
||||
processingElement_mealy_not2 inp = mealy processingElement (0,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
|
||||
|
||||
--out1 inp = processingElement_mealy_not2 (queue_mealy2 inp)
|
||||
|
||||
--out inp = queue_mealy1 (processingElement_mealy_not1 inp)
|
||||
|
||||
--out1 inp = processingElement_mealy_not2 (queue_mealy1 (processingElement_mealy_not1 inp))
|
||||
|
||||
not_of_not inp = queue_mealy2 (processingElement_mealy_not2 (queue_mealy1 (processingElement_mealy_not1 inp)))
|
||||
|
||||
topEntity
|
||||
:: Clock System
|
||||
-> Reset System
|
||||
-> Enable System
|
||||
-> Signal System Bool
|
||||
-> Signal System Bool
|
||||
topEntity = exposeClockResetEnable not_of_not
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module ProcessingElement where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
size=5
|
||||
processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size))
|
||||
processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where
|
||||
currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t)
|
||||
| otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)
|
||||
|
||||
--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f))
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
-- mealy functions have type: current_state -> input -> (new_state, output)
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
module Queue where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2))
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
module Queue30 where
|
||||
import Clash.Explicit.Testbench
|
||||
import Clash.Prelude
|
||||
|
||||
f (x,y) = x
|
||||
g (x,y) = y
|
||||
|
||||
-- 1 = True
|
||||
-- (-1) = False
|
||||
-- 0 = Maybe
|
||||
|
||||
modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)
|
||||
| (index<= tt2) && (index>= tt1) = 1
|
||||
| (index<= ff2) && (index>= ff1) = (-1)
|
||||
| (index<= mm2) && (index>= mm1) = 0
|
||||
| (index<= tm2) && (index>= tm1) && (value == 0) = 1
|
||||
| (index<= fm2) && (index>= fm1) && (value == 0) = (-1)
|
||||
| otherwise = value
|
||||
|
||||
modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec
|
||||
|
||||
queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool)
|
||||
|
||||
queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue)
|
||||
where
|
||||
headposnvalue
|
||||
| (vec !! (length vec -1) ==1) = True
|
||||
| otherwise = False
|
||||
(tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23)
|
||||
|
||||
queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)))
|
||||
|
||||
queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp
|
||||
|
||||
--import qualified Data.List as L
|
||||
-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ]
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package Prop_combined_topEntity_types is
|
||||
|
||||
|
||||
type Tup5 is record
|
||||
Tup5_sel0_boolean_0 : boolean;
|
||||
Tup5_sel1_boolean_1 : boolean;
|
||||
Tup5_sel2_boolean_2 : boolean;
|
||||
Tup5_sel3_boolean_3 : boolean;
|
||||
Tup5_sel4_boolean_4 : boolean;
|
||||
end record;
|
||||
subtype rst_System is std_logic;
|
||||
type Tup6 is record
|
||||
Tup6_sel0_boolean_0 : boolean;
|
||||
Tup6_sel1_boolean_1 : boolean;
|
||||
Tup6_sel2_boolean_2 : boolean;
|
||||
Tup6_sel3_boolean_3 : boolean;
|
||||
Tup6_sel4_boolean_4 : boolean;
|
||||
Tup6_sel5_boolean_5 : boolean;
|
||||
end record;
|
||||
subtype en_System is boolean;
|
||||
type Tup10 is record
|
||||
Tup10_sel0_unsigned_0 : unsigned(4 downto 0);
|
||||
Tup10_sel1_unsigned_1 : unsigned(4 downto 0);
|
||||
Tup10_sel2_unsigned_2 : unsigned(4 downto 0);
|
||||
Tup10_sel3_unsigned_3 : unsigned(4 downto 0);
|
||||
Tup10_sel4_unsigned_4 : unsigned(4 downto 0);
|
||||
Tup10_sel5_unsigned_5 : unsigned(4 downto 0);
|
||||
Tup10_sel6_unsigned_6 : unsigned(4 downto 0);
|
||||
Tup10_sel7_unsigned_7 : unsigned(4 downto 0);
|
||||
Tup10_sel8_unsigned_8 : unsigned(4 downto 0);
|
||||
Tup10_sel9_unsigned_9 : unsigned(4 downto 0);
|
||||
end record;
|
||||
type Tup3 is record
|
||||
Tup3_sel0_unsigned : unsigned(0 downto 0);
|
||||
Tup3_sel1_Tup10_0 : Tup10;
|
||||
Tup3_sel2_Tup10_1 : Tup10;
|
||||
end record;
|
||||
subtype clk_System is std_logic;
|
||||
|
||||
type Tup2_0 is record
|
||||
Tup2_0_sel0_Tup3 : Tup3;
|
||||
Tup2_0_sel1_Tup10 : Tup10;
|
||||
end record;
|
||||
type array_of_signed_2 is array (integer range <>) of signed(1 downto 0);
|
||||
type Tup2_1 is record
|
||||
Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 0);
|
||||
Tup2_1_sel1_boolean : boolean;
|
||||
end record;
|
||||
type Tup2_3 is record
|
||||
Tup2_3_sel0_array_of_signed_2 : array_of_signed_2(0 to 11);
|
||||
Tup2_3_sel1_boolean : boolean;
|
||||
end record;
|
||||
type Tup2_4 is record
|
||||
Tup2_4_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 19);
|
||||
Tup2_4_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0);
|
||||
end record;
|
||||
type Tup2_2 is record
|
||||
Tup2_2_sel0_array_of_signed_2 : array_of_signed_2(0 to 6);
|
||||
Tup2_2_sel1_boolean : boolean;
|
||||
end record;
|
||||
type Tup2 is record
|
||||
Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 19);
|
||||
Tup2_sel1_boolean : boolean;
|
||||
end record;
|
||||
type Tup2_6 is record
|
||||
Tup2_6_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 6);
|
||||
Tup2_6_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0);
|
||||
end record;
|
||||
type Tup2_7 is record
|
||||
Tup2_7_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 11);
|
||||
Tup2_7_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0);
|
||||
end record;
|
||||
type Tup2_5 is record
|
||||
Tup2_5_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0);
|
||||
Tup2_5_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0);
|
||||
end record;
|
||||
function toSLV (b : in boolean) return std_logic_vector;
|
||||
function fromSLV (sl : in std_logic_vector) return boolean;
|
||||
function tagToEnum (s : in signed) return boolean;
|
||||
function dataToTag (b : in boolean) return signed;
|
||||
function toSLV (u : in unsigned) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return unsigned;
|
||||
function toSLV (p : Tup5) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup5;
|
||||
function toSLV (sl : in std_logic) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return std_logic;
|
||||
function toSLV (p : Tup6) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup6;
|
||||
function toSLV (p : Tup10) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup10;
|
||||
function toSLV (p : Tup3) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup3;
|
||||
function toSLV (s : in signed) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return signed;
|
||||
function toSLV (p : Tup2_0) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_0;
|
||||
function toSLV (value : array_of_signed_2) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return array_of_signed_2;
|
||||
function toSLV (p : Tup2_1) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_1;
|
||||
function toSLV (p : Tup2_3) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_3;
|
||||
function toSLV (p : Tup2_4) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_4;
|
||||
function toSLV (p : Tup2_2) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_2;
|
||||
function toSLV (p : Tup2) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2;
|
||||
function toSLV (p : Tup2_6) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_6;
|
||||
function toSLV (p : Tup2_7) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_7;
|
||||
function toSLV (p : Tup2_5) return std_logic_vector;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_5;
|
||||
end;
|
||||
|
||||
package body Prop_combined_topEntity_types is
|
||||
function toSLV (b : in boolean) return std_logic_vector is
|
||||
begin
|
||||
if b then
|
||||
return "1";
|
||||
else
|
||||
return "0";
|
||||
end if;
|
||||
end;
|
||||
function fromSLV (sl : in std_logic_vector) return boolean is
|
||||
begin
|
||||
if sl = "1" then
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
end if;
|
||||
end;
|
||||
function tagToEnum (s : in signed) return boolean is
|
||||
begin
|
||||
if s = to_signed(0,64) then
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
end if;
|
||||
end;
|
||||
function dataToTag (b : in boolean) return signed is
|
||||
begin
|
||||
if b then
|
||||
return to_signed(1,64);
|
||||
else
|
||||
return to_signed(0,64);
|
||||
end if;
|
||||
end;
|
||||
function toSLV (u : in unsigned) return std_logic_vector is
|
||||
begin
|
||||
return std_logic_vector(u);
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return unsigned is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return unsigned(islv);
|
||||
end;
|
||||
function toSLV (p : Tup5) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup5_sel0_boolean_0) & toSLV(p.Tup5_sel1_boolean_1) & toSLV(p.Tup5_sel2_boolean_2) & toSLV(p.Tup5_sel3_boolean_3) & toSLV(p.Tup5_sel4_boolean_4));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup5 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1)),fromSLV(islv(2 to 2)),fromSLV(islv(3 to 3)),fromSLV(islv(4 to 4)));
|
||||
end;
|
||||
function toSLV (sl : in std_logic) return std_logic_vector is
|
||||
begin
|
||||
return std_logic_vector'(0 => sl);
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return std_logic is
|
||||
alias islv : std_logic_vector (0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return islv(0);
|
||||
end;
|
||||
function toSLV (p : Tup6) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup6_sel0_boolean_0) & toSLV(p.Tup6_sel1_boolean_1) & toSLV(p.Tup6_sel2_boolean_2) & toSLV(p.Tup6_sel3_boolean_3) & toSLV(p.Tup6_sel4_boolean_4) & toSLV(p.Tup6_sel5_boolean_5));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup6 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1)),fromSLV(islv(2 to 2)),fromSLV(islv(3 to 3)),fromSLV(islv(4 to 4)),fromSLV(islv(5 to 5)));
|
||||
end;
|
||||
function toSLV (p : Tup10) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup10 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49)));
|
||||
end;
|
||||
function toSLV (p : Tup3) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup3 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100)));
|
||||
end;
|
||||
function toSLV (s : in signed) return std_logic_vector is
|
||||
begin
|
||||
return std_logic_vector(s);
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return signed is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return signed(islv);
|
||||
end;
|
||||
function toSLV (p : Tup2_0) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_0 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150)));
|
||||
end;
|
||||
function toSLV (value : array_of_signed_2) return std_logic_vector is
|
||||
alias ivalue : array_of_signed_2(1 to value'length) is value;
|
||||
variable result : std_logic_vector(1 to value'length * 2);
|
||||
begin
|
||||
for i in ivalue'range loop
|
||||
result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i));
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
variable result : array_of_signed_2(0 to slv'length / 2 - 1);
|
||||
begin
|
||||
for i in result'range loop
|
||||
result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1));
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
function toSLV (p : Tup2_1) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_1 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2)));
|
||||
end;
|
||||
function toSLV (p : Tup2_3) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_3_sel0_array_of_signed_2) & toSLV(p.Tup2_3_sel1_boolean));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_3 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 24)));
|
||||
end;
|
||||
function toSLV (p : Tup2_4) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_4_sel0_array_of_signed_2_0) & toSLV(p.Tup2_4_sel1_array_of_signed_2_1));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_4 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 39)),fromSLV(islv(40 to 41)));
|
||||
end;
|
||||
function toSLV (p : Tup2_2) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_2_sel0_array_of_signed_2) & toSLV(p.Tup2_2_sel1_boolean));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_2 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 14)));
|
||||
end;
|
||||
function toSLV (p : Tup2) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 39)),fromSLV(islv(40 to 40)));
|
||||
end;
|
||||
function toSLV (p : Tup2_6) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_6_sel0_array_of_signed_2_0) & toSLV(p.Tup2_6_sel1_array_of_signed_2_1));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_6 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 15)));
|
||||
end;
|
||||
function toSLV (p : Tup2_7) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_7_sel0_array_of_signed_2_0) & toSLV(p.Tup2_7_sel1_array_of_signed_2_1));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_7 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 25)));
|
||||
end;
|
||||
function toSLV (p : Tup2_5) return std_logic_vector is
|
||||
begin
|
||||
return (toSLV(p.Tup2_5_sel0_array_of_signed_2_0) & toSLV(p.Tup2_5_sel1_array_of_signed_2_1));
|
||||
end;
|
||||
function fromSLV (slv : in std_logic_vector) return Tup2_5 is
|
||||
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
|
||||
begin
|
||||
return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3)));
|
||||
end;
|
||||
end;
|
||||
|
||||