969 lines
41 KiB
VHDL
969 lines
41 KiB
VHDL
-- Automatically generated VHDL-93
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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use std.textio.all;
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use work.all;
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use work.Prop2_testBench_types.all;
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use testBench_slv2string_FD7FE0FDE5409B5E.all;
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entity testBench is
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port(result : out boolean);
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end;
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architecture structural of testBench is
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signal \c$ds_app_arg\ : Prop2_testBench_types.index_16;
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signal \c$ds_app_arg_0\ : boolean;
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signal s : Prop2_testBench_types.index_16 := to_unsigned(0,4);
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-- prop2.hs:36:5-7
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signal \Prop2.testBench_clk\ : Prop2_testBench_types.clk_System;
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signal z : Prop2_testBench_types.index_57;
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signal result_1 : Prop2_testBench_types.index_29;
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signal \c$ds_app_arg_1\ : boolean;
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signal \c$result_rec\ : boolean;
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signal s_0 : Prop2_testBench_types.index_29 := to_unsigned(0,5);
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signal f2 : boolean;
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signal \f'\ : boolean := false;
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-- prop2.hs:10:1-43
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signal \c$ds_app_arg_2\ : Prop2_testBench_types.array_of_signed_2(0 to 0) := Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2));
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signal result_2 : boolean;
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signal \c$case_alt\ : signed(1 downto 0);
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signal \c$case_alt_0\ : signed(1 downto 0);
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signal \c$case_alt_1\ : signed(1 downto 0);
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signal \c$case_alt_2\ : signed(1 downto 0);
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signal \c$case_alt_3\ : signed(1 downto 0);
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-- Queue.hs:20:1-12
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signal fm1 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal fm2 : unsigned(4 downto 0);
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signal \c$app_arg\ : boolean;
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-- Queue.hs:20:1-12
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signal tm1 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal tm2 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal mm1 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal mm2 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal ff1 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal ff2 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal tt1 : unsigned(4 downto 0);
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-- Queue.hs:20:1-12
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signal tt2 : unsigned(4 downto 0);
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signal \c$app_arg_0\ : signed(1 downto 0);
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signal result_3 : Prop2_testBench_types.Tup2;
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-- prop2.hs:12:1-124
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signal \c$ds_app_arg_3\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1)
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, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(0,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
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, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(0,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(0,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
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signal result_4 : Prop2_testBench_types.Tup10;
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signal result_5 : Prop2_testBench_types.Tup2_0;
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-- ProcessingElement.hs:9:1-777
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signal opcode : unsigned(0 downto 0);
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-- ProcessingElement.hs:9:1-777
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signal ds4 : Prop2_testBench_types.Tup10;
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-- prop2.hs:8:1-76
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signal \c$ds_app_arg_4\ : Prop2_testBench_types.array_of_signed_2(0 to 11) := Prop2_testBench_types.array_of_signed_2'( to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2) );
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signal result_6 : boolean;
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signal \c$app_arg_1\ : Prop2_testBench_types.array_of_signed_2(0 to 11);
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signal \c$app_arg_2\ : signed(1 downto 0);
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signal result_7 : Prop2_testBench_types.Tup2_1;
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-- prop2.hs:16:1-124
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signal \c$ds_app_arg_5\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1)
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, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(0,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(0,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(11,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(11,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
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, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(7,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(11,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(0,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(0,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
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signal result_8 : Prop2_testBench_types.Tup10;
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signal result_9 : Prop2_testBench_types.Tup2_0;
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-- ProcessingElement.hs:9:1-777
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signal opcode_0 : unsigned(0 downto 0);
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-- ProcessingElement.hs:9:1-777
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signal ds4_0 : Prop2_testBench_types.Tup10;
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-- prop2.hs:8:1-76
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signal \c$ds_app_arg_6\ : Prop2_testBench_types.array_of_signed_2(0 to 11) := Prop2_testBench_types.array_of_signed_2'( to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2)
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, to_signed(0,2) );
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signal result_10 : boolean;
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signal \c$app_arg_3\ : Prop2_testBench_types.array_of_signed_2(0 to 11);
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signal \c$app_arg_4\ : signed(1 downto 0);
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signal result_11 : Prop2_testBench_types.Tup2_1;
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-- prop2.hs:14:1-125
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signal \c$ds_app_arg_7\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1)
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, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(0,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(0,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
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, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5)
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, Tup10_sel1_unsigned_1 => to_unsigned(0,5)
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, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
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, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
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, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
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, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
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, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
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, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
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, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
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, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
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signal result_12 : Prop2_testBench_types.Tup10;
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signal result_13 : Prop2_testBench_types.Tup2_0;
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-- ProcessingElement.hs:9:1-777
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signal opcode_1 : unsigned(0 downto 0);
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-- ProcessingElement.hs:9:1-777
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signal ds4_1 : Prop2_testBench_types.Tup10;
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signal \c$ds_app_arg_8\ : Prop2_testBench_types.index_17;
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signal \c$ds_app_arg_9\ : boolean;
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signal s_1 : Prop2_testBench_types.index_17 := to_unsigned(0,5);
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-- prop2.hs:29:1-9
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signal \c$Prop2.testBench_app_arg\ : Prop2_testBench_types.rst_System;
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signal \c$ds_app_arg_selection_res\ : boolean;
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signal \c$vec\ : Prop2_testBench_types.array_of_boolean(0 to 15);
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signal result_selection_res : boolean;
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signal \c$vec_0\ : Prop2_testBench_types.array_of_boolean(0 to 28);
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signal \c$case_alt_selection_res\ : boolean;
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signal \c$case_alt_selection_res_0\ : boolean;
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signal \c$case_alt_selection_res_1\ : boolean;
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signal \c$case_alt_selection_res_2\ : boolean;
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signal \c$case_alt_selection_res_3\ : boolean;
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signal \c$vec_1\ : Prop2_testBench_types.array_of_signed_2(0 to 1);
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signal \c$case_alt_sel_alt_9\ : Prop2_testBench_types.Tup2_2;
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signal \c$vec_2\ : Prop2_testBench_types.array_of_signed_2(0 to 1);
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signal \c$app_arg_7\ : Prop2_testBench_types.Tup2_2;
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signal ds4_selection_res : boolean;
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signal \c$vec_3\ : Prop2_testBench_types.array_of_signed_2(0 to 12);
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signal \c$app_arg_1_1\ : Prop2_testBench_types.Tup2_3;
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signal \c$vec_4\ : Prop2_testBench_types.array_of_signed_2(0 to 11);
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signal ds4_selection_res_0 : boolean;
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signal \c$vec_5\ : Prop2_testBench_types.array_of_signed_2(0 to 12);
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signal \c$app_arg_3_3\ : Prop2_testBench_types.Tup2_3;
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signal \c$vec_6\ : Prop2_testBench_types.array_of_signed_2(0 to 11);
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signal ds4_selection_res_1 : boolean;
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signal \c$ds_app_arg_selection_res_0\ : boolean;
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signal \c$vec_7\ : Prop2_testBench_types.array_of_boolean(0 to 16);
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begin
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\c$ds_app_arg_selection_res\ <= s < to_unsigned(15,4);
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\c$ds_app_arg\ <= s + to_unsigned(1,4) when \c$ds_app_arg_selection_res\ else
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s;
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\c$vec\ <= Prop2_testBench_types.array_of_boolean'( true
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false );
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-- index begin
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indexVec : block
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signal vec_index : integer range 0 to 16-1;
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begin
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vec_index <= to_integer((signed(std_logic_vector(resize(s,64)))))
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-- pragma translate_off
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mod 16
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-- pragma translate_on
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;
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\c$ds_app_arg_0\ <= \c$vec\(vec_index);
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end block;
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-- index end
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-- register begin
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s_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
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begin
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if \c$Prop2.testBench_app_arg\ = '1' then
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s <= to_unsigned(0,4);
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elsif rising_edge(\Prop2.testBench_clk\) then
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s <= \c$ds_app_arg\;
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end if;
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end process;
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-- register end
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-- tbClockGen begin
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-- pragma translate_off
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clkGen : process is
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constant half_periodH : time := 10000000 fs / 2;
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constant half_periodL : time := 10000000 fs - half_periodH;
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begin
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\Prop2.testBench_clk\ <= '0';
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wait for 10000 ps;
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while (not \c$result_rec\) loop
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\Prop2.testBench_clk\ <= not \Prop2.testBench_clk\;
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wait for half_periodH;
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\Prop2.testBench_clk\ <= not \Prop2.testBench_clk\;
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wait for half_periodL;
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end loop;
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wait;
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end process;
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-- pragma translate_on
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-- tbClockGen end
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z <= resize(s_0,6) + resize(to_unsigned(1,5),6);
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result_selection_res <= z > to_unsigned(28,6);
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result_1 <= to_unsigned(28,5) when result_selection_res else
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resize(z,5);
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\c$vec_0\ <= Prop2_testBench_types.array_of_boolean'( false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, false
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true
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, true );
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-- index begin
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indexVec_0 : block
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signal vec_index_0 : integer range 0 to 29-1;
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begin
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vec_index_0 <= to_integer((signed(std_logic_vector(resize(s_0,64)))))
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-- pragma translate_off
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mod 29
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-- pragma translate_on
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;
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\c$ds_app_arg_1\ <= \c$vec_0\(vec_index_0);
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end block;
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-- index end
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\c$result_rec\ <= \f'\ when \f'\ else
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f2;
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-- register begin
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s_0_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
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begin
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if \c$Prop2.testBench_app_arg\ = '1' then
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s_0 <= to_unsigned(0,5);
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elsif rising_edge(\Prop2.testBench_clk\) then
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s_0 <= result_1;
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end if;
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end process;
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-- register end
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-- assert begin
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r_assert : block
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-- pragma translate_off
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signal actual : boolean;
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signal expected : boolean;
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-- pragma translate_on
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begin
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-- pragma translate_off
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actual <= result_2;
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expected <= \c$ds_app_arg_1\;
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process(\Prop2.testBench_clk\) is
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begin
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if (rising_edge(\Prop2.testBench_clk\)) then
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assert (toSLV(actual) = toSLV(expected)) report (("outputVerifier") & ", expected: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(expected)) & ", actual: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(actual))) severity error;
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end if;
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end process;
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-- pragma translate_on
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f2 <= \f'\;
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end block;
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-- assert end
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-- register begin
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f_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
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begin
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if \c$Prop2.testBench_app_arg\ = '1' then
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\f'\ <= false;
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elsif rising_edge(\Prop2.testBench_clk\) then
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\f'\ <= (s_0 = to_unsigned(28,5));
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end if;
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end process;
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-- register end
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-- register begin
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cds_app_arg_2_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
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begin
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if \c$Prop2.testBench_app_arg\ = '1' then
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\c$ds_app_arg_2\ <= Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2));
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elsif rising_edge(\Prop2.testBench_clk\) then
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\c$ds_app_arg_2\ <= result_3.Tup2_sel0_array_of_signed_2;
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end if;
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end process;
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-- register end
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result_2 <= result_3.Tup2_sel1_boolean;
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\c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1);
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\c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else
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\c$case_alt_0\;
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\c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1);
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\c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else
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\c$case_alt_1\;
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\c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1);
|
|
|
|
\c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else
|
|
\c$case_alt_2\;
|
|
|
|
\c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\);
|
|
|
|
\c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else
|
|
\c$case_alt_3\;
|
|
|
|
\c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\);
|
|
|
|
\c$vec_1\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\)));
|
|
|
|
\c$case_alt_sel_alt_9\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high));
|
|
|
|
\c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else
|
|
\c$case_alt_sel_alt_9\.Tup2_2_sel0_array_of_signed_2_0(0);
|
|
|
|
fm1 <= result_4.Tup10_sel8_unsigned_8;
|
|
|
|
fm2 <= result_4.Tup10_sel9_unsigned_9;
|
|
|
|
\c$vec_2\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\)));
|
|
|
|
\c$app_arg_7\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high));
|
|
|
|
\c$app_arg\ <= \c$app_arg_7\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2);
|
|
|
|
tm1 <= result_4.Tup10_sel6_unsigned_6;
|
|
|
|
tm2 <= result_4.Tup10_sel7_unsigned_7;
|
|
|
|
mm1 <= result_4.Tup10_sel4_unsigned_4;
|
|
|
|
mm2 <= result_4.Tup10_sel5_unsigned_5;
|
|
|
|
ff1 <= result_4.Tup10_sel2_unsigned_2;
|
|
|
|
ff2 <= result_4.Tup10_sel3_unsigned_3;
|
|
|
|
tt1 <= result_4.Tup10_sel0_unsigned_0;
|
|
|
|
tt2 <= result_4.Tup10_sel1_unsigned_1;
|
|
|
|
-- index begin
|
|
indexVec_1 : block
|
|
signal vec_index_1 : integer range 0 to 1-1;
|
|
begin
|
|
vec_index_1 <= to_integer(to_signed(0,64))
|
|
-- pragma translate_off
|
|
mod 1
|
|
-- pragma translate_on
|
|
;
|
|
\c$app_arg_0\ <= \c$ds_app_arg_2\(vec_index_1);
|
|
end block;
|
|
-- index end
|
|
|
|
result_3 <= ( Tup2_sel0_array_of_signed_2 => Prop2_testBench_types.array_of_signed_2'(0 => \c$case_alt\)
|
|
, Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) );
|
|
|
|
-- register begin
|
|
cds_app_arg_3_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
\c$ds_app_arg_3\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1)
|
|
, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(0,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
|
|
, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(0,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(0,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
\c$ds_app_arg_3\ <= result_5.Tup2_0_sel0_Tup3;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
result_4 <= result_5.Tup2_0_sel1_Tup10;
|
|
|
|
result_5 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_3\
|
|
, Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0
|
|
, Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1
|
|
, Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2
|
|
, Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3
|
|
, Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4
|
|
, Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5
|
|
, Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6
|
|
, Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7
|
|
, Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8
|
|
, Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) );
|
|
|
|
opcode <= \c$ds_app_arg_3\.Tup3_sel0_unsigned;
|
|
|
|
ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_10 or result_6)) or ((opcode = to_unsigned(1,1)) and result_10);
|
|
|
|
ds4 <= \c$ds_app_arg_3\.Tup3_sel1_Tup10_0 when ds4_selection_res else
|
|
\c$ds_app_arg_3\.Tup3_sel2_Tup10_1;
|
|
|
|
-- register begin
|
|
cds_app_arg_4_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
\c$ds_app_arg_4\ <= Prop2_testBench_types.array_of_signed_2'( to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2) );
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
\c$ds_app_arg_4\ <= result_7.Tup2_1_sel0_array_of_signed_2;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
result_6 <= result_7.Tup2_1_sel1_boolean;
|
|
|
|
\c$vec_3\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\)));
|
|
|
|
\c$app_arg_1_1\ <= (\c$vec_3\(0 to 12-1),\c$vec_3\(12 to \c$vec_3\'high));
|
|
|
|
\c$vec_4\ <= \c$app_arg_1_1\.Tup2_3_sel0_array_of_signed_2_0;
|
|
|
|
-- imap begin
|
|
imap : block
|
|
function max (l,r : in natural) return natural is
|
|
begin
|
|
if l > r then return l;
|
|
else return r;
|
|
end if;
|
|
end function;
|
|
begin
|
|
imap_0 : for i in \c$app_arg_1\'range generate
|
|
begin
|
|
fun_1 : block
|
|
signal \c$app_arg_8\ : signed(63 downto 0);
|
|
signal \c$case_alt_7\ : signed(1 downto 0);
|
|
signal \c$case_alt_8\ : signed(1 downto 0);
|
|
signal \c$case_alt_9\ : signed(1 downto 0);
|
|
signal \c$case_alt_10\ : signed(1 downto 0);
|
|
signal \c$case_alt_11\ : signed(1 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal fm1_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal fm2_1 : unsigned(4 downto 0);
|
|
signal \c$app_arg_9\ : boolean;
|
|
-- Queue.hs:20:1-12
|
|
signal tm1_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tm2_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal mm1_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal mm2_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal ff1_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal ff2_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tt1_1 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tt2_1 : unsigned(4 downto 0);
|
|
signal \c$case_alt_selection_res_4\ : boolean;
|
|
signal \c$case_alt_selection_res_5\ : boolean;
|
|
signal \c$case_alt_selection_res_6\ : boolean;
|
|
signal \c$case_alt_selection_res_7\ : boolean;
|
|
signal \c$case_alt_selection_res_8\ : boolean;
|
|
begin
|
|
\c$app_arg_1\(i) <= \c$case_alt_7\;
|
|
|
|
\c$app_arg_8\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(12)))))),64)));
|
|
|
|
\c$case_alt_selection_res_4\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tt2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tt1_1);
|
|
|
|
\c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else
|
|
\c$case_alt_8\;
|
|
|
|
\c$case_alt_selection_res_5\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= ff2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= ff1_1);
|
|
|
|
\c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else
|
|
\c$case_alt_9\;
|
|
|
|
\c$case_alt_selection_res_6\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= mm2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= mm1_1);
|
|
|
|
\c$case_alt_9\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else
|
|
\c$case_alt_10\;
|
|
|
|
\c$case_alt_selection_res_7\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tm1_1) and \c$app_arg_9\);
|
|
|
|
\c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else
|
|
\c$case_alt_11\;
|
|
|
|
\c$case_alt_selection_res_8\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= fm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= fm1_1) and \c$app_arg_9\);
|
|
|
|
\c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else
|
|
\c$vec_4\(i);
|
|
|
|
fm1_1 <= result_8.Tup10_sel8_unsigned_8;
|
|
|
|
fm2_1 <= result_8.Tup10_sel9_unsigned_9;
|
|
|
|
\c$app_arg_9\ <= \c$vec_4\(i) = to_signed(0,2);
|
|
|
|
tm1_1 <= result_8.Tup10_sel6_unsigned_6;
|
|
|
|
tm2_1 <= result_8.Tup10_sel7_unsigned_7;
|
|
|
|
mm1_1 <= result_8.Tup10_sel4_unsigned_4;
|
|
|
|
mm2_1 <= result_8.Tup10_sel5_unsigned_5;
|
|
|
|
ff1_1 <= result_8.Tup10_sel2_unsigned_2;
|
|
|
|
ff2_1 <= result_8.Tup10_sel3_unsigned_3;
|
|
|
|
tt1_1 <= result_8.Tup10_sel0_unsigned_0;
|
|
|
|
tt2_1 <= result_8.Tup10_sel1_unsigned_1;
|
|
|
|
|
|
end block;
|
|
end generate;
|
|
end block;
|
|
-- imap end
|
|
|
|
-- index begin
|
|
indexVec_2 : block
|
|
signal vec_index_2 : integer range 0 to 12-1;
|
|
begin
|
|
vec_index_2 <= to_integer(to_signed(11,64))
|
|
-- pragma translate_off
|
|
mod 12
|
|
-- pragma translate_on
|
|
;
|
|
\c$app_arg_2\ <= \c$ds_app_arg_4\(vec_index_2);
|
|
end block;
|
|
-- index end
|
|
|
|
result_7 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_1\
|
|
, Tup2_1_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) );
|
|
|
|
-- register begin
|
|
cds_app_arg_5_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
\c$ds_app_arg_5\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1)
|
|
, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(0,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(0,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(11,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(11,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
|
|
, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(7,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(11,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(0,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(0,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
\c$ds_app_arg_5\ <= result_9.Tup2_0_sel0_Tup3;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
result_8 <= result_9.Tup2_0_sel1_Tup10;
|
|
|
|
result_9 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_5\
|
|
, Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0
|
|
, Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1
|
|
, Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2
|
|
, Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3
|
|
, Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4
|
|
, Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5
|
|
, Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6
|
|
, Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7
|
|
, Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8
|
|
, Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) );
|
|
|
|
opcode_0 <= \c$ds_app_arg_5\.Tup3_sel0_unsigned;
|
|
|
|
ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (\c$ds_app_arg_9\ or \c$ds_app_arg_9\)) or ((opcode_0 = to_unsigned(1,1)) and \c$ds_app_arg_9\);
|
|
|
|
ds4_0 <= \c$ds_app_arg_5\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else
|
|
\c$ds_app_arg_5\.Tup3_sel2_Tup10_1;
|
|
|
|
-- register begin
|
|
cds_app_arg_6_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
\c$ds_app_arg_6\ <= Prop2_testBench_types.array_of_signed_2'( to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2)
|
|
, to_signed(0,2) );
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
\c$ds_app_arg_6\ <= result_11.Tup2_1_sel0_array_of_signed_2;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
result_10 <= result_11.Tup2_1_sel1_boolean;
|
|
|
|
\c$vec_5\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\)));
|
|
|
|
\c$app_arg_3_3\ <= (\c$vec_5\(0 to 12-1),\c$vec_5\(12 to \c$vec_5\'high));
|
|
|
|
\c$vec_6\ <= \c$app_arg_3_3\.Tup2_3_sel0_array_of_signed_2_0;
|
|
|
|
-- imap begin
|
|
imap_1 : block
|
|
function max_0 (l,r : in natural) return natural is
|
|
begin
|
|
if l > r then return l;
|
|
else return r;
|
|
end if;
|
|
end function;
|
|
begin
|
|
imap_2 : for i_0 in \c$app_arg_3\'range generate
|
|
begin
|
|
fun_2 : block
|
|
signal \c$app_arg_10\ : signed(63 downto 0);
|
|
signal \c$case_alt_12\ : signed(1 downto 0);
|
|
signal \c$case_alt_13\ : signed(1 downto 0);
|
|
signal \c$case_alt_14\ : signed(1 downto 0);
|
|
signal \c$case_alt_15\ : signed(1 downto 0);
|
|
signal \c$case_alt_16\ : signed(1 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal fm1_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal fm2_2 : unsigned(4 downto 0);
|
|
signal \c$app_arg_11\ : boolean;
|
|
-- Queue.hs:20:1-12
|
|
signal tm1_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tm2_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal mm1_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal mm2_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal ff1_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal ff2_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tt1_2 : unsigned(4 downto 0);
|
|
-- Queue.hs:20:1-12
|
|
signal tt2_2 : unsigned(4 downto 0);
|
|
signal \c$case_alt_selection_res_9\ : boolean;
|
|
signal \c$case_alt_selection_res_10\ : boolean;
|
|
signal \c$case_alt_selection_res_11\ : boolean;
|
|
signal \c$case_alt_selection_res_12\ : boolean;
|
|
signal \c$case_alt_selection_res_13\ : boolean;
|
|
begin
|
|
\c$app_arg_3\(i_0) <= \c$case_alt_12\;
|
|
|
|
\c$app_arg_10\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(12)))))),64)));
|
|
|
|
\c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tt2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tt1_2);
|
|
|
|
\c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else
|
|
\c$case_alt_13\;
|
|
|
|
\c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= ff2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= ff1_2);
|
|
|
|
\c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else
|
|
\c$case_alt_14\;
|
|
|
|
\c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= mm2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= mm1_2);
|
|
|
|
\c$case_alt_14\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else
|
|
\c$case_alt_15\;
|
|
|
|
\c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tm1_2) and \c$app_arg_11\);
|
|
|
|
\c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else
|
|
\c$case_alt_16\;
|
|
|
|
\c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= fm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= fm1_2) and \c$app_arg_11\);
|
|
|
|
\c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else
|
|
\c$vec_6\(i_0);
|
|
|
|
fm1_2 <= result_12.Tup10_sel8_unsigned_8;
|
|
|
|
fm2_2 <= result_12.Tup10_sel9_unsigned_9;
|
|
|
|
\c$app_arg_11\ <= \c$vec_6\(i_0) = to_signed(0,2);
|
|
|
|
tm1_2 <= result_12.Tup10_sel6_unsigned_6;
|
|
|
|
tm2_2 <= result_12.Tup10_sel7_unsigned_7;
|
|
|
|
mm1_2 <= result_12.Tup10_sel4_unsigned_4;
|
|
|
|
mm2_2 <= result_12.Tup10_sel5_unsigned_5;
|
|
|
|
ff1_2 <= result_12.Tup10_sel2_unsigned_2;
|
|
|
|
ff2_2 <= result_12.Tup10_sel3_unsigned_3;
|
|
|
|
tt1_2 <= result_12.Tup10_sel0_unsigned_0;
|
|
|
|
tt2_2 <= result_12.Tup10_sel1_unsigned_1;
|
|
|
|
|
|
end block;
|
|
end generate;
|
|
end block;
|
|
-- imap end
|
|
|
|
-- index begin
|
|
indexVec_3 : block
|
|
signal vec_index_3 : integer range 0 to 12-1;
|
|
begin
|
|
vec_index_3 <= to_integer(to_signed(11,64))
|
|
-- pragma translate_off
|
|
mod 12
|
|
-- pragma translate_on
|
|
;
|
|
\c$app_arg_4\ <= \c$ds_app_arg_6\(vec_index_3);
|
|
end block;
|
|
-- index end
|
|
|
|
result_11 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_3\
|
|
, Tup2_1_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) );
|
|
|
|
-- register begin
|
|
cds_app_arg_7_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
\c$ds_app_arg_7\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1)
|
|
, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(31,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(0,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(0,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) )
|
|
, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5)
|
|
, Tup10_sel1_unsigned_1 => to_unsigned(0,5)
|
|
, Tup10_sel2_unsigned_2 => to_unsigned(31,5)
|
|
, Tup10_sel3_unsigned_3 => to_unsigned(31,5)
|
|
, Tup10_sel4_unsigned_4 => to_unsigned(31,5)
|
|
, Tup10_sel5_unsigned_5 => to_unsigned(31,5)
|
|
, Tup10_sel6_unsigned_6 => to_unsigned(31,5)
|
|
, Tup10_sel7_unsigned_7 => to_unsigned(31,5)
|
|
, Tup10_sel8_unsigned_8 => to_unsigned(31,5)
|
|
, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) );
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
\c$ds_app_arg_7\ <= result_13.Tup2_0_sel0_Tup3;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
result_12 <= result_13.Tup2_0_sel1_Tup10;
|
|
|
|
result_13 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_7\
|
|
, Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0
|
|
, Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1
|
|
, Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2
|
|
, Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3
|
|
, Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4
|
|
, Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5
|
|
, Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6
|
|
, Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7
|
|
, Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8
|
|
, Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) );
|
|
|
|
opcode_1 <= \c$ds_app_arg_7\.Tup3_sel0_unsigned;
|
|
|
|
ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_0\)) or ((opcode_1 = to_unsigned(1,1)) and \c$ds_app_arg_0\);
|
|
|
|
ds4_1 <= \c$ds_app_arg_7\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else
|
|
\c$ds_app_arg_7\.Tup3_sel2_Tup10_1;
|
|
|
|
\c$ds_app_arg_selection_res_0\ <= s_1 < to_unsigned(16,5);
|
|
|
|
\c$ds_app_arg_8\ <= s_1 + to_unsigned(1,5) when \c$ds_app_arg_selection_res_0\ else
|
|
s_1;
|
|
|
|
\c$vec_7\ <= Prop2_testBench_types.array_of_boolean'( false
|
|
, false
|
|
, false
|
|
, false
|
|
, false
|
|
, false
|
|
, false
|
|
, true
|
|
, true
|
|
, true
|
|
, true
|
|
, true
|
|
, true
|
|
, true
|
|
, false
|
|
, false
|
|
, false );
|
|
|
|
-- index begin
|
|
indexVec_4 : block
|
|
signal vec_index_4 : integer range 0 to 17-1;
|
|
begin
|
|
vec_index_4 <= to_integer((signed(std_logic_vector(resize(s_1,64)))))
|
|
-- pragma translate_off
|
|
mod 17
|
|
-- pragma translate_on
|
|
;
|
|
\c$ds_app_arg_9\ <= \c$vec_7\(vec_index_4);
|
|
end block;
|
|
-- index end
|
|
|
|
-- register begin
|
|
s_1_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\)
|
|
begin
|
|
if \c$Prop2.testBench_app_arg\ = '1' then
|
|
s_1 <= to_unsigned(0,5);
|
|
elsif rising_edge(\Prop2.testBench_clk\) then
|
|
s_1 <= \c$ds_app_arg_8\;
|
|
end if;
|
|
end process;
|
|
-- register end
|
|
|
|
-- resetGen begin
|
|
resetGen : block
|
|
constant reset_delay : time := 10000 ps - 1 ps + (integer'(1) * 10000 ps);
|
|
begin
|
|
-- pragma translate_off
|
|
\c$Prop2.testBench_app_arg\
|
|
<= '1',
|
|
'0' after reset_delay;
|
|
-- pragma translate_on
|
|
end block;
|
|
-- resetGen end
|
|
|
|
result <= \c$result_rec\;
|
|
|
|
|
|
end;
|
|
|