diff --git a/src/MTL2Clash_tool/MTL2Clash.py b/src/MTL2Clash_tool/MTL2Clash.py new file mode 100644 index 0000000..642399d --- /dev/null +++ b/src/MTL2Clash_tool/MTL2Clash.py @@ -0,0 +1,292 @@ +import sys + +ap_count = 0 + +file_write = ["module Prop where\nimport Clash.Prelude\nimport ProcessingElement(processingElement)\nimport Queue(queue,queuetest)\nimport Queue30(queue30,queuetest30)\n\n"] +tt_temp = {'!':["not","(1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31))"], + 'G':["box","(1,(31,31,31,31,0,0,t2,t2,31,31),(31,31,t1,t2,0,0,31,31,31,31))"], + 'F':["diamond","(1,(t1,t2,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,t2,t2))"], + 'H':["box","(1,(31,31,31,31,0,0,t2,t2,31,31),(31,31,0,t2,0,0,31,31,31,31))"], + 'E':["diamond","(1,(0,t2,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,t2,t2))"], + 'X':["next","(1,(1,1,31,31,0,0,31,31,31,31),(31,31,1,1,0,0,31,31,31,31))"], + 'v':["or","(0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31))"], + 'U':["(1,(31,31,31,31,0,0,31,31,31,31),(31,31,0,t1-1,31,31,31,31,31,31))", + "(1,(31,31,31,31,31,31,t1,t2,31,31),(31,31,31,31,31,31,31,31,t2,t2))", + "(0,(31,31,31,31,31,31,31,31,31,31),(31,31,31,31,31,31,31,31,t1,t2))"]} + + +class node: + def __init__(self,val,left=None,right=None,t1=0,t2=0,isbinary=0,isunary=0,isap=0,q_no=0,q_mealy="",pe_mealy=""): + self.val=val + self.left=left + self.right=right + self.t1 = t1 + self.t2 = t2 + self.isbinary = isbinary + self.isunary = isunary + self.isap = isap + self.q_no = q_no + self.q_mealy = q_mealy + self.pe_mealy = pe_mealy + +def precedence(op): + if op == '!': + return 11 + elif op == 'G': + return 10 + elif op == 'H': + return 9 + elif op == 'F': + return 8 + elif op == 'E': + return 7 + elif op == 'X': + return 6 + elif op == 'U': + return 5 + elif op == '^': + return 4 + elif op == 'v': + return 3 + elif op == '>': + return 2 + else: + return 1 + +root = [node('')] + +def construc_tree(r,expr): + cur = r + parent = [] + i = 0 + while i < len(expr): + if expr[i] in ['E','H','X','!','G','F']: + cur.isunary = 1 + if expr[i] in ['E','H']: + cur.t1 = 0 + cur.t2 = int(expr[i+1]) + elif expr[i] in ['G','F']: + temp = expr[i:-1].index(']')+i + cur.t1, cur.t2 = map(int , expr[i+2:temp].split(',')) + elif expr[i] in ['U','^','v','>']: + cur.isbinary = 1 + if expr[i] in ['G','F','U']: + temp = expr[i:-1].index(']')+i + cur.t1, cur.t2 = map(int , expr[i+2:temp].split(',')) + if expr[i] in ['^','v','>','U','G','F','H','E','U','X','!']: + # first check the precedence of the operator to his parent operator + # if the precedence of the operator is less than the parent operator + # then pop till the parent operator and make it the left child of the operator + # if the parent is empty then make the operator as the root + # if the parent is not empty then make the operator as the right child of the parent + # and make the parent as the parent of the operator + # make the operator as the current node + par = None + ch = False + + while parent and (precedence(expr[i]) < precedence(parent[-1].val)): + par = parent.pop() + ch = True + + if ch: + new = node(expr[i]) + if parent: + temp = parent[-1].right + parent[-1].right = new + new.left = temp + else: + new.left = root[0] + root[0] = new + + parent.append(new) + new.right = node('') + cur = new.right + else: + cur.val = expr[i] + cur.right = node('') + parent.append(cur) + cur = cur.right + else: + if expr[i].isalpha(): + cur.left = node(expr[i]) + cur.left.isap = 1 + + i =i+ 1 + + +def manage_implies_and(root): + if root != None and root != "": + manage_implies_and(root.left) + manage_implies_and(root.right) + if root.val == '>': + new = node('!') + new.isunary = 1 + root.val = 'v' + root.isbinary = 1 + new.left = root.left + elif root.val == '^': + new1 = node('!') + new1.isunary = 1 + new2 = node('!') + new2.isunary = 1 + new3 = node('v') + new3.isbinary = 1 + root.val = '!' + new1.left = root.left + new2.left = root.right + new3.left = new1 + new3.right = new2 + root.left = new3 + root.isbinary = 0 + root.isunary = 1 + root.right = None + + +file = "property.txt" +f = open(file, "r") +data = f.readlines() +ex = data[0][:-1] +construc_tree(root[0],ex) +manage_implies_and(root[0]) + +Q_ID = 1 + +def post_order(root): + global Q_ID + global ap_count + if root != None: + post_order(root.left) + post_order(root.right) + if root != None and root != "" and (not (root.isap == 0 and root.isbinary == 0 and root.isunary == 0)) and (root.val != ""): + print("-" + root.val+"-") + print(root.t1) + print(root.t2) + print(root.isap) + print(root.isunary) + print(root.isbinary) + + if root.isap == 0: + t = '0:>Nil' + t1 = "" + for x in range(root.t2): + t2 = "0:>" + t1 = t1 + t2 + t = t1+t + if root.val != 'U': + print("queue_mealy_"+str(Q_ID)+" inp = mealy queue ("+t+") inp") + file_write.append("queue_mealy_"+str(Q_ID)+" inp = mealy queue ("+t+") inp\n") + + elif root.val == 'U': + print("queue_mealy_"+str(Q_ID)+" inp = mealy queue30 ("+t+") inp") + file_write.append("queue_mealy_"+str(Q_ID)+" inp = mealy queue30 ("+t+") inp\n") + root.q_mealy = "queue_mealy_"+str(Q_ID) + root.q_no = Q_ID + Q_ID+=1 + elif root.isap == 1: + print('inp'+root.val) + root.q_mealy = 'inp'+root.val + ap_count+=1 + + if root.val in ['H','E']: + tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2)) + elif root.val in ['G','F']: + tt_temp[root.val][1] = tt_temp[root.val][1].replace("t1",str(root.t1)) + tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2)) + elif root.val in ['U']: + tt_temp[root.val][0] = tt_temp[root.val][0].replace("t1-1",str(root.t1-1)) + tt_temp[root.val][1] = tt_temp[root.val][1].replace("t1",str(root.t1)) + tt_temp[root.val][1] = tt_temp[root.val][1].replace("t2",str(root.t2)) + tt_temp[root.val][2] = tt_temp[root.val][2].replace("t1",str(root.t1)) + tt_temp[root.val][2] = tt_temp[root.val][2].replace("t2",str(root.t2)) + + if root.isap == 0: + if root.val != 'U': + file_write.append("processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no)+" inp = mealy processingElement "+tt_temp[root.val][1] +" inp\n\n") + print("processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no)+" inp = mealy processingElement "+tt_temp[root.val][1] +" inp\n") + root.pe_mealy = "processingElement_mealy_"+tt_temp[root.val][0]+str(root.q_no) + elif root.val == 'U': + file_write.append("processingElement_mealy_until1"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][0]+" inp\n") + file_write.append("processingElement_mealy_until2"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][1]+" inp\n") + file_write.append("processingElement_mealy_until3"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][2]+" inp\n\n") + file_write.append("until_out"+str(root.q_no)+" (inp1,inp2) = "+root.q_mealy+" (bundle (processingElement_mealy_until1"+str(root.q_no)+" (bundle ( inp1, inp1)), processingElement_mealy_until2"+str(root.q_no)+" (bundle ( inp2, inp2)), processingElement_mealy_until3"+str(root.q_no)+" (bundle ( inp1, inp2))))\n\n") + print("processingElement_mealy_until1"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][0]+" inp") + print("processingElement_mealy_until2"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][1]+" inp") + print("processingElement_mealy_until3"+str(root.q_no)+" inp = mealy processingElement "+ tt_temp[root.val][2]+" inp\n") + print("until_out"+str(root.q_no)+" (inp1,inp2) = "+root.q_mealy+" (bundle (processingElement_mealy_until1"+str(root.q_no)+" (bundle ( inp1, inp1)), processingElement_mealy_until2"+str(root.q_no)+" (bundle ( inp2, inp2)), processingElement_mealy_until3"+str(root.q_no)+" (bundle ( inp1, inp2))))\n") + root.pe_mealy = "until_out"+str(root.q_no) + elif root.isap == 1: + print('inp'+root.val) + root.pe_mealy = 'inp'+root.val + print('\n') + + +post_order(root[0]) + +prop = "" + +def final_prop(root): + if root != None and root != "" and (not (root.isap == 0 and root.isbinary == 0 and root.isunary == 0)) and (root.val != ""): + if root.val != 'U': + if root.isap == 1: + return(root.pe_mealy) + elif root.isunary == 1: + if root.left != None: + return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.left) + ") , (" + final_prop(root.left) + ") ) ) )") + if root.right != None: + return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.right) + ") , (" + final_prop(root.right) + ") ) ) )") + elif root.isbinary == 1: + return(root.q_mealy + " ( " + root.pe_mealy + " ( bundle ( (" + final_prop(root.left) + ") , (" + final_prop(root.right) + ") ) ) )") + elif root.val == 'U': + return(root.pe_mealy+" ( "+"("+final_prop(root.left)+") , ("+final_prop(root.right)+") )") + elif root != None and root.val == "": + if root.left != None: + return(final_prop(root.left)) + + else: + return(final_prop(root.right)) + else: + return("") + + +property = "prop (" + +def prop_lhs(root): + global property + if root != None and root != "": + prop_lhs(root.left) + prop_lhs(root.right) + if root.isap == 1: + property = property + "inp"+root.val+"," + +prop_lhs(root[0]) + +#https://stackoverflow.com/questions/423379/using-global-variables-in-a-function +def replacer(s, newstring, index, nofail=False): + # raise an error if index is outside of the string + if not nofail and index not in range(len(s)): + raise ValueError("index outside given string") + # if not erroring, but the index is still not in the correct range.. + if index < 0: # add it to the beginning + return newstring + s + if index > len(s): # add it to the end + return s + newstring + # insert the new string between "slices" of the original + return s[:index] + newstring + s[index + 1:] + +property = replacer(property,') = ',len(property)-1) + +property = property + final_prop(root[0]) + '\n\n' +file_write.append(property) +print(property) + +n_ips = "" +for i in range(ap_count): + if ap_count-1 == i: + n_ips = n_ips + "Signal System (Bool)" + else: + n_ips = "Signal System (Bool)" + " , " + n_ips +file_write.append("topEntity\n :: Clock System\n -> Reset System\n -> Enable System\n -> ("+n_ips+")\n -> Signal System ( Bool)\ntopEntity = exposeClockResetEnable prop\n\n") + +f = open("Prop.hs", "w") +f.writelines(file_write) +f.close() \ No newline at end of file diff --git a/src/MTL2Clash_tool/ProcessingElement.hs b/src/MTL2Clash_tool/ProcessingElement.hs new file mode 100644 index 0000000..14ccafb --- /dev/null +++ b/src/MTL2Clash_tool/ProcessingElement.hs @@ -0,0 +1,23 @@ +module ProcessingElement where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +size=5 +processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) +processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where + currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t) + | otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f) + +--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) +--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +-- mealy functions have type: current_state -> input -> (new_state, output) diff --git a/src/MTL2Clash_tool/Prop.hs b/src/MTL2Clash_tool/Prop.hs new file mode 100644 index 0000000..9c0b160 --- /dev/null +++ b/src/MTL2Clash_tool/Prop.hs @@ -0,0 +1,25 @@ +module Prop where +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +queue_mealy_1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp +processingElement_mealy_A inp = mealy processingElement (1,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +queue_mealy_2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp +processingElement_mealy_box2 inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp + +queue_mealy_3 inp = mealy queue (0:>Nil) inp +processingElement_mealy_or3 inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +prop (inpA,inpB) = queue_mealy_3 ( processingElement_mealy_or3 ( bundle ( (( queue_mealy_1 ( processingElement_mealy_A ( bundle ( inpA , inpA )) ) )) , (queue_mealy_2 ( processingElement_mealy_box2 ( bundle ( (inpB) , (inpB) ) ) )) ) ) ) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool) , Signal System (Bool)) + -> Signal System ( Bool) +topEntity = exposeClockResetEnable prop + diff --git a/src/MTL2Clash_tool/Queue.hs b/src/MTL2Clash_tool/Queue.hs new file mode 100644 index 0000000..03d8ace --- /dev/null +++ b/src/MTL2Clash_tool/Queue.hs @@ -0,0 +1,30 @@ +module Queue where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool) + +queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) diff --git a/src/MTL2Clash_tool/Queue30.hs b/src/MTL2Clash_tool/Queue30.hs new file mode 100644 index 0000000..96778a8 --- /dev/null +++ b/src/MTL2Clash_tool/Queue30.hs @@ -0,0 +1,36 @@ +module Queue30 where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool) + +queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23) + +queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))) + +queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp + +--import qualified Data.List as L +-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ] diff --git a/src/MTL2Clash_tool/property.txt b/src/MTL2Clash_tool/property.txt new file mode 100644 index 0000000..aa509e2 --- /dev/null +++ b/src/MTL2Clash_tool/property.txt @@ -0,0 +1 @@ +AvG[2,5]B diff --git a/src/hardware/ProcessingElement.hs b/src/hardware/ProcessingElement.hs new file mode 100644 index 0000000..14ccafb --- /dev/null +++ b/src/hardware/ProcessingElement.hs @@ -0,0 +1,23 @@ +module ProcessingElement where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +size=5 +processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) +processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where + currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t) + | otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f) + +--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) +--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +-- mealy functions have type: current_state -> input -> (new_state, output) diff --git a/src/hardware/Queue.hs b/src/hardware/Queue.hs new file mode 100644 index 0000000..03d8ace --- /dev/null +++ b/src/hardware/Queue.hs @@ -0,0 +1,30 @@ +module Queue where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool) + +queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) diff --git a/src/hardware/Queue30.hs b/src/hardware/Queue30.hs new file mode 100644 index 0000000..96778a8 --- /dev/null +++ b/src/hardware/Queue30.hs @@ -0,0 +1,36 @@ +module Queue30 where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool) + +queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23) + +queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))) + +queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp + +--import qualified Data.List as L +-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ] diff --git a/tests/MTL_Examples/Operators.hs b/tests/MTL_Examples/Operators.hs new file mode 100644 index 0000000..a20b732 --- /dev/null +++ b/tests/MTL_Examples/Operators.hs @@ -0,0 +1,53 @@ +module Operators where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +f (x,y) = x +g (x,y) = y + +queue_mealy11 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>Nil) inp +-- in until1 '1 --> t1-1' +processingElement_mealy_until1 inp = mealy processingElement (1,(31,31,31,31,0,0,31,31,31,31),(31,31,0,1,31,31,31,31,31,31)) inp +processingElement_mealy_until2 inp = mealy processingElement (1,(31,31,31,31,31,31,2,5,31,31),(31,31,31,31,31,31,31,31,5,5)) inp +processingElement_mealy_until3 inp = mealy processingElement (0,(31,31,31,31,31,31,31,31,31,31),(31,31,31,31,31,31,31,31,2,5)) inp +until_out (inp1,inp2) = queue_mealy11 (bundle (processingElement_mealy_until1 (bundle ( inp1, inp1)), processingElement_mealy_until2 (bundle ( inp2, inp2)), processingElement_mealy_until3 (bundle ( inp1, inp2)))) + +queue_mealy1 inp = mealy queue (0:>0:>0:>0:>1:>0:>Nil) inp +queue_mealy2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy3 inp = mealy queue (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp +or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1, inp2))) + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp +not_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_not (bundle ( inp1, inp2))) + +processingElement_mealy_box3 inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp +box_out inp1 =queue_mealy2 (processingElement_mealy_box3 (bundle ( inp1, inp1))) + +prop (inp1,inp2) = until_out (inp1 , (queue_mealy2 (processingElement_mealy_box3 (bundle (inp2,inp2))))) + +processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp +diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1, inp2))) + +--topEntity +-- :: Clock System +-- -> Reset System +-- -> Enable System +-- -> (Signal System (Bool), Signal System (Bool)) +-- -> Signal System (Vec 6 (Signed 2), Bool) +--topEntity = exposeClockResetEnable until_out + +--testBench :: Signal System Bool +--testBench = done +-- where +-- testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) +-- testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False]) +-- expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)]) +-- done = expectOutput (topEntity clk rst en (testInput1, testInput2)) +-- en = enableGen +-- clk = tbSystemClockGen (not <$> done) +-- rst = systemResetGen diff --git a/tests/MTL_Examples/Operators_2.hs b/tests/MTL_Examples/Operators_2.hs new file mode 100644 index 0000000..12a6b08 --- /dev/null +++ b/tests/MTL_Examples/Operators_2.hs @@ -0,0 +1,43 @@ +module Operators where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) + +f (x,y) = x +g (x,y) = y + +queue_mealy1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy2 inp = mealy queuetest (0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy3 inp = mealy queuetest (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp +or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1, inp2))) + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp +not_out inp1 =queue_mealy3 (processingElement_mealy_not (bundle ( inp1, inp1))) + +processingElement_mealy_box inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp +box_out inp1 =queue_mealy2 (processingElement_mealy_box (bundle ( inp1, inp1))) + +processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp +diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1, inp2))) + +--topEntity +-- :: Clock System +-- -> Reset System +-- -> Enable System +-- -> (Signal System (Bool)) +-- -> Signal System (Vec 6 (Signed 2), Bool) +--topEntity = exposeClockResetEnable box_out + +--testBench :: Signal System Bool +--testBench = done +-- where +-- testInput1 = stimuliGenerator clk rst $(listToVecTH [True::Bool , False, False, False, False, True, False, False, True, True, True, True, False]) +-- testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False]) +-- expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)]) +-- done = expectOutput (topEntity clk rst en (testInput1, testInput2)) +-- en = enableGen +-- clk = tbSystemClockGen (not <$> done) +-- rst = systemResetGen diff --git a/tests/MTL_Examples/ProcessingElement.hs b/tests/MTL_Examples/ProcessingElement.hs new file mode 100644 index 0000000..14ccafb --- /dev/null +++ b/tests/MTL_Examples/ProcessingElement.hs @@ -0,0 +1,23 @@ +module ProcessingElement where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +size=5 +processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) +processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where + currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t) + | otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f) + +--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) +--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +-- mealy functions have type: current_state -> input -> (new_state, output) diff --git a/tests/MTL_Examples/Queue.hs b/tests/MTL_Examples/Queue.hs new file mode 100644 index 0000000..03d8ace --- /dev/null +++ b/tests/MTL_Examples/Queue.hs @@ -0,0 +1,30 @@ +module Queue where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool) + +queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) diff --git a/tests/MTL_Examples/Queue30.hs b/tests/MTL_Examples/Queue30.hs new file mode 100644 index 0000000..96778a8 --- /dev/null +++ b/tests/MTL_Examples/Queue30.hs @@ -0,0 +1,36 @@ +module Queue30 where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool) + +queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23) + +queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))) + +queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp + +--import qualified Data.List as L +-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ] diff --git a/tests/MTL_Examples/notofnot.hs b/tests/MTL_Examples/notofnot.hs new file mode 100644 index 0000000..22f8b27 --- /dev/null +++ b/tests/MTL_Examples/notofnot.hs @@ -0,0 +1,31 @@ +module Notofnot where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) + +f (x,y) = x +g (x,y) = y + +queue_mealy1 inp = mealy queue (0:>Nil) inp +--size=5 +--queue_mealy2 :: HiddenClockResetEnable dom => Signal dom (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> Signal dom Bool +queue_mealy2 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp +processingElement_mealy_not1 inp = mealy processingElement (0,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp +processingElement_mealy_not2 inp = mealy processingElement (0,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp + +--out1 inp = processingElement_mealy_not2 (queue_mealy2 inp) + +--out inp = queue_mealy1 (processingElement_mealy_not1 inp) + +--out1 inp = processingElement_mealy_not2 (queue_mealy1 (processingElement_mealy_not1 inp)) + +not_of_not inp = queue_mealy2 (processingElement_mealy_not2 (queue_mealy1 (processingElement_mealy_not1 inp))) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> Signal System Bool + -> Signal System Bool +topEntity = exposeClockResetEnable not_of_not diff --git a/tests/washing_machine/properties/ProcessingElement.hs b/tests/washing_machine/properties/ProcessingElement.hs new file mode 100644 index 0000000..14ccafb --- /dev/null +++ b/tests/washing_machine/properties/ProcessingElement.hs @@ -0,0 +1,23 @@ +module ProcessingElement where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +size=5 +processingElement:: (Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) -> (Bool,Bool) -> ((Unsigned 1,(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)),(Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size,Unsigned size)) +processingElement (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) (input1,input2) = (currInst',(tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) where + currInst'= (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | ((opcode ==0) && (input1||input2)) || ((opcode ==1) && (input1)) = (tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t) + | otherwise = (tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f) + +--currInst = (opcode,QID1,QID2,DQID,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) +--currInst = (opcode,(tt1t, tt2t, ff1t, ff2t, mm1t, mm2t, tm1t, tm2t, fm1t, fm2t),(tt1f, tt2f, ff1f, ff2f, mm1f, mm2f, tm1f, tm2f, fm1f, fm2f)) + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +-- mealy functions have type: current_state -> input -> (new_state, output) diff --git a/tests/washing_machine/properties/Queue.hs b/tests/washing_machine/properties/Queue.hs new file mode 100644 index 0000000..03d8ace --- /dev/null +++ b/tests/washing_machine/properties/Queue.hs @@ -0,0 +1,30 @@ +module Queue where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +queue :: (KnownNat n) => Vec n (Signed 2) -> (Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5) -> (Vec n (Signed 2),Bool) + +queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queuetest vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = (f (queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)), queue vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) diff --git a/tests/washing_machine/properties/Queue30.hs b/tests/washing_machine/properties/Queue30.hs new file mode 100644 index 0000000..96778a8 --- /dev/null +++ b/tests/washing_machine/properties/Queue30.hs @@ -0,0 +1,36 @@ +module Queue30 where +import Clash.Explicit.Testbench +import Clash.Prelude + +f (x,y) = x +g (x,y) = y + +-- 1 = True +-- (-1) = False +-- 0 = Maybe + +modEveryElem index value (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) + | (index<= tt2) && (index>= tt1) = 1 + | (index<= ff2) && (index>= ff1) = (-1) + | (index<= mm2) && (index>= mm1) = 0 + | (index<= tm2) && (index>= tm1) && (value == 0) = 1 + | (index<= fm2) && (index>= fm1) && (value == 0) = (-1) + | otherwise = value + +modify vec (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2) = imap (\i a -> modEveryElem (fromIntegral i) a (tt1, tt2, ff1, ff2, mm1, mm2, tm1, tm2, fm1, fm2)) vec + +queue30 :: (KnownNat n) => Vec n (Signed 2) -> ((Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5),(Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5,Unsigned 5)) -> (Vec n (Signed 2),Bool) + +queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (modify (f (shiftInAt0 vec (0:>Nil))) (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2'), headposnvalue) + where + headposnvalue + | (vec !! (length vec -1) ==1) = True + | otherwise = False + (tt1', tt2', ff1', ff2', mm1', mm2', tm1', tm2', fm1', fm2') = (min (min tt11 tt12) tt13,min (min tt21 tt22) tt23, min (min ff11 ff12) ff13,min (min ff21 ff22) ff23, min (min mm11 mm12) mm13,min (min mm21 mm22) mm23, min (min tm11 tm12) tm13,min (min tm21 tm22) tm23, min (min fm11 fm12) fm13,min (min fm21 fm22) fm23) + +queuetest30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23)) = (f (queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))), queue30 vec ((tt11, tt21, ff11, ff21, mm11, mm21, tm11, tm21, fm11, fm21),(tt12, tt22, ff12, ff22, mm12, mm22, tm12, tm22, fm12, fm22),(tt13, tt23, ff13, ff23, mm13, mm23, tm13, tm23, fm13, fm23))) + +queue_mealy30 inp = mealy queuetest30 (0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp + +--import qualified Data.List as L +-- L.take 15 $ simulate @System queue_mealy30 [ ((1,3,4,5,0,0,15,15,15,15), (15,15,15,15,15,15,15,15,15,15), (0,0,15,15,15,15,15,15,15,15)),((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ,((15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7),(15,15, 15,15,15,15, 5,5,7,7)) ] diff --git a/tests/washing_machine/properties/all_props_combined/Prop_combined_topEntity_types.vhdl b/tests/washing_machine/properties/all_props_combined/Prop_combined_topEntity_types.vhdl new file mode 100644 index 0000000..1a60af8 --- /dev/null +++ b/tests/washing_machine/properties/all_props_combined/Prop_combined_topEntity_types.vhdl @@ -0,0 +1,317 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop_combined_topEntity_types is + + + type Tup5 is record + Tup5_sel0_boolean_0 : boolean; + Tup5_sel1_boolean_1 : boolean; + Tup5_sel2_boolean_2 : boolean; + Tup5_sel3_boolean_3 : boolean; + Tup5_sel4_boolean_4 : boolean; + end record; + subtype rst_System is std_logic; + type Tup6 is record + Tup6_sel0_boolean_0 : boolean; + Tup6_sel1_boolean_1 : boolean; + Tup6_sel2_boolean_2 : boolean; + Tup6_sel3_boolean_3 : boolean; + Tup6_sel4_boolean_4 : boolean; + Tup6_sel5_boolean_5 : boolean; + end record; + subtype en_System is boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_1_sel1_boolean : boolean; + end record; + type Tup2_3 is record + Tup2_3_sel0_array_of_signed_2 : array_of_signed_2(0 to 11); + Tup2_3_sel1_boolean : boolean; + end record; + type Tup2_4 is record + Tup2_4_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 19); + Tup2_4_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2_2 is record + Tup2_2_sel0_array_of_signed_2 : array_of_signed_2(0 to 6); + Tup2_2_sel1_boolean : boolean; + end record; + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 19); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_6 is record + Tup2_6_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 6); + Tup2_6_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2_7 is record + Tup2_7_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 11); + Tup2_7_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2_5 is record + Tup2_5_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_5_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (p : Tup5) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup5; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (p : Tup6) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup6; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (p : Tup2_3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_3; + function toSLV (p : Tup2_4) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_4; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_6) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_6; + function toSLV (p : Tup2_7) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_7; + function toSLV (p : Tup2_5) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_5; +end; + +package body Prop_combined_topEntity_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (p : Tup5) return std_logic_vector is + begin + return (toSLV(p.Tup5_sel0_boolean_0) & toSLV(p.Tup5_sel1_boolean_1) & toSLV(p.Tup5_sel2_boolean_2) & toSLV(p.Tup5_sel3_boolean_3) & toSLV(p.Tup5_sel4_boolean_4)); + end; + function fromSLV (slv : in std_logic_vector) return Tup5 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1)),fromSLV(islv(2 to 2)),fromSLV(islv(3 to 3)),fromSLV(islv(4 to 4))); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (p : Tup6) return std_logic_vector is + begin + return (toSLV(p.Tup6_sel0_boolean_0) & toSLV(p.Tup6_sel1_boolean_1) & toSLV(p.Tup6_sel2_boolean_2) & toSLV(p.Tup6_sel3_boolean_3) & toSLV(p.Tup6_sel4_boolean_4) & toSLV(p.Tup6_sel5_boolean_5)); + end; + function fromSLV (slv : in std_logic_vector) return Tup6 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1)),fromSLV(islv(2 to 2)),fromSLV(islv(3 to 3)),fromSLV(islv(4 to 4)),fromSLV(islv(5 to 5))); + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_3) return std_logic_vector is + begin + return (toSLV(p.Tup2_3_sel0_array_of_signed_2) & toSLV(p.Tup2_3_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 24))); + end; + function toSLV (p : Tup2_4) return std_logic_vector is + begin + return (toSLV(p.Tup2_4_sel0_array_of_signed_2_0) & toSLV(p.Tup2_4_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_4 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 39)),fromSLV(islv(40 to 41))); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_array_of_signed_2) & toSLV(p.Tup2_2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 14))); + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 39)),fromSLV(islv(40 to 40))); + end; + function toSLV (p : Tup2_6) return std_logic_vector is + begin + return (toSLV(p.Tup2_6_sel0_array_of_signed_2_0) & toSLV(p.Tup2_6_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_6 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 15))); + end; + function toSLV (p : Tup2_7) return std_logic_vector is + begin + return (toSLV(p.Tup2_7_sel0_array_of_signed_2_0) & toSLV(p.Tup2_7_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_7 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 25))); + end; + function toSLV (p : Tup2_5) return std_logic_vector is + begin + return (toSLV(p.Tup2_5_sel0_array_of_signed_2_0) & toSLV(p.Tup2_5_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_5 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/all_props_combined/prop_combined.hs b/tests/washing_machine/properties/all_props_combined/prop_combined.hs new file mode 100644 index 0000000..0b984e1 --- /dev/null +++ b/tests/washing_machine/properties/all_props_combined/prop_combined.hs @@ -0,0 +1,33 @@ +module Prop_combined where +import Clash.Explicit.Testbench +import Clash.Prelude +import Prop1(prop1) +import Prop2(prop2) +import Prop3(prop3) +import Prop4(prop4) +import Prop5(prop5) + +finalprop (drain,dry,start,wash,fill,soak) = bundle (prop1 (drain,dry) , prop2 (start, wash), prop3 (fill, soak), prop4 (start,soak), prop5 (start, dry) ) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool), Signal System (Bool), Signal System (Bool), Signal System (Bool),Signal System (Bool),Signal System (Bool)) + -> (Signal System (Bool,Bool,Bool,Bool,Bool)) +topEntity = exposeClockResetEnable finalprop + +testBench :: Signal System Bool +testBench = done + where + testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False]) + testInput3 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + testInput4 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + testInput5 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + testInput6 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + expectOutput = outputVerifier' clk rst $(listToVecTH [(False,False, True , True, False) ::(Bool,Bool,Bool,Bool,Bool), (True, True, False, True, True), (False, False, False, False, True)]) + done = expectOutput (topEntity clk rst en (testInput1, testInput2,testInput3,testInput4,testInput5,testInput6)) + en = enableGen + clk = tbSystemClockGen (not <$> done) + rst = systemResetGen diff --git a/tests/washing_machine/properties/all_props_combined/topEntity.vhdl b/tests/washing_machine/properties/all_props_combined/topEntity.vhdl new file mode 100644 index 0000000..d3f20c8 --- /dev/null +++ b/tests/washing_machine/properties/all_props_combined/topEntity.vhdl @@ -0,0 +1,3712 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop_combined_topEntity_types.all; + +entity topEntity is + port(-- clock + clk : in Prop_combined_topEntity_types.clk_System; + -- reset + rst : in Prop_combined_topEntity_types.rst_System; + -- enable + en : in Prop_combined_topEntity_types.en_System; + eta1_0 : in boolean; + eta1_1 : in boolean; + eta1_2 : in boolean; + eta1_3 : in boolean; + eta1_4 : in boolean; + eta1_5 : in boolean; + ccase_alt_0 : out boolean; + ccase_alt_1 : out boolean; + ccase_alt_2 : out boolean; + ccase_alt_3 : out boolean; + ccase_alt_4 : out boolean); +end; + +architecture structural of topEntity is + -- prop_combined.hs:10:1-154 + signal drain : boolean; + -- prop_combined.hs:10:1-154 + signal dry : boolean; + -- prop_combined.hs:10:1-154 + signal start : boolean; + -- prop_combined.hs:10:1-154 + signal wash : boolean; + -- prop_combined.hs:10:1-154 + signal fill : boolean; + -- prop_combined.hs:10:1-154 + signal soak : boolean; + -- Prop5.hs:8:1-103 + signal \c$ds_app_arg\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 19) := Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result : boolean; + -- Queue30.hs:26:1-7 + signal \c$tt1_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tt1_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tt2_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tt2_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$ff1_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$ff1_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$ff2_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$ff2_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$mm1_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$mm1_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$mm2_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$mm2_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tm1_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tm1_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tm2_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$tm2_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$fm1_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$fm1_case_alt_0\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$fm2_case_alt\ : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal \c$fm2_case_alt_0\ : unsigned(4 downto 0); + signal result_0 : Prop_combined_topEntity_types.array_of_signed_2(0 to 19); + signal \c$app_arg\ : signed(1 downto 0); + signal \c$case_alt\ : Prop_combined_topEntity_types.Tup2; + -- Queue30.hs:26:1-7 + signal tt11 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt21 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff11 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff21 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm11 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm21 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm11 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm21 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm11 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm21 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt12 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt22 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff12 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff22 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm12 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm22 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm12 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm22 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm12 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm22 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt13 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt23 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff13 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff23 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm13 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm23 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm13 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm23 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm13 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm23 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm2 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal fm1 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm2 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tm1 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm2 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal mm1 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff2 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal ff1 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt2 : unsigned(4 downto 0); + -- Queue30.hs:26:1-7 + signal tt1 : unsigned(4 downto 0); + -- Prop5.hs:11:1-131 + signal \c$ds_app_arg_0\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(0,5) +, Tup10_sel9_unsigned_9 => to_unsigned(19,5) ) ); + signal result_1 : Prop_combined_topEntity_types.Tup10; + signal result_2 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop_combined_topEntity_types.Tup10; + -- Prop5.hs:10:1-131 + signal \c$ds_app_arg_1\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(0,5) +, Tup10_sel7_unsigned_7 => to_unsigned(19,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(19,5) +, Tup10_sel9_unsigned_9 => to_unsigned(19,5) ) ); + signal result_3 : Prop_combined_topEntity_types.Tup10; + signal result_4 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop_combined_topEntity_types.Tup10; + -- Prop5.hs:9:1-128 + signal \c$ds_app_arg_2\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_5 : Prop_combined_topEntity_types.Tup10; + signal result_6 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop_combined_topEntity_types.Tup10; + -- Prop4.hs:10:1-45 + signal \c$ds_app_arg_3\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_7 : boolean; + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + signal \c$case_alt_4\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_0 : unsigned(4 downto 0); + signal \c$app_arg_0\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_0 : unsigned(4 downto 0); + signal \c$app_arg_1\ : signed(1 downto 0); + signal result_8 : Prop_combined_topEntity_types.Tup2_1; + -- Prop4.hs:12:1-124 + signal \c$ds_app_arg_4\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_9 : Prop_combined_topEntity_types.Tup10; + signal result_10 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_2 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_2 : Prop_combined_topEntity_types.Tup10; + -- Prop4.hs:8:1-63 + signal \c$ds_app_arg_5\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6) := Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_11 : boolean; + signal \c$app_arg_2\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6); + signal \c$app_arg_3\ : signed(1 downto 0); + signal result_12 : Prop_combined_topEntity_types.Tup2_2; + -- Prop4.hs:16:1-125 + signal \c$ds_app_arg_6\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) +, Tup10_sel1_unsigned_1 => to_unsigned(6,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(6,5) +, Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + signal result_13 : Prop_combined_topEntity_types.Tup10; + signal result_14 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_3 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_3 : Prop_combined_topEntity_types.Tup10; + -- Prop4.hs:8:1-63 + signal \c$ds_app_arg_7\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6) := Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_15 : boolean; + signal \c$app_arg_4\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6); + signal \c$app_arg_5\ : signed(1 downto 0); + signal result_16 : Prop_combined_topEntity_types.Tup2_2; + -- Prop4.hs:14:1-125 + signal \c$ds_app_arg_8\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_17 : Prop_combined_topEntity_types.Tup10; + signal result_18 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_4 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_4 : Prop_combined_topEntity_types.Tup10; + -- Prop3.hs:8:1-44 + signal \c$ds_app_arg_9\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_19 : boolean; + signal \c$case_alt_5\ : signed(1 downto 0); + signal \c$case_alt_6\ : signed(1 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + signal \c$case_alt_9\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_6\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$app_arg_7\ : signed(1 downto 0); + signal result_20 : Prop_combined_topEntity_types.Tup2_1; + -- Prop3.hs:13:1-124 + signal \c$ds_app_arg_10\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_21 : Prop_combined_topEntity_types.Tup10; + signal result_22 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_5 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_5 : Prop_combined_topEntity_types.Tup10; + -- Prop3.hs:8:1-44 + signal \c$ds_app_arg_11\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_23 : boolean; + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + signal \c$case_alt_14\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_8\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$app_arg_9\ : signed(1 downto 0); + signal result_24 : Prop_combined_topEntity_types.Tup2_1; + -- Prop3.hs:17:1-122 + signal \c$ds_app_arg_12\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) +, Tup10_sel1_unsigned_1 => to_unsigned(1,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(1,5) +, Tup10_sel3_unsigned_3 => to_unsigned(1,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_25 : Prop_combined_topEntity_types.Tup10; + signal result_26 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_6 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_6 : Prop_combined_topEntity_types.Tup10; + -- Prop3.hs:8:1-44 + signal \c$ds_app_arg_13\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_27 : boolean; + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + signal \c$case_alt_17\ : signed(1 downto 0); + signal \c$case_alt_18\ : signed(1 downto 0); + signal \c$case_alt_19\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_3 : unsigned(4 downto 0); + signal \c$app_arg_10\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_3 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_3 : unsigned(4 downto 0); + signal \c$app_arg_11\ : signed(1 downto 0); + signal result_28 : Prop_combined_topEntity_types.Tup2_1; + -- Prop3.hs:13:1-124 + signal \c$ds_app_arg_14\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_29 : Prop_combined_topEntity_types.Tup10; + signal result_30 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_7 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_7 : Prop_combined_topEntity_types.Tup10; + -- Prop3.hs:8:1-44 + signal \c$ds_app_arg_15\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_31 : boolean; + signal \c$case_alt_20\ : signed(1 downto 0); + signal \c$case_alt_21\ : signed(1 downto 0); + signal \c$case_alt_22\ : signed(1 downto 0); + signal \c$case_alt_23\ : signed(1 downto 0); + signal \c$case_alt_24\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_4 : unsigned(4 downto 0); + signal \c$app_arg_12\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_4 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_4 : unsigned(4 downto 0); + signal \c$app_arg_13\ : signed(1 downto 0); + signal result_32 : Prop_combined_topEntity_types.Tup2_1; + -- Prop3.hs:15:1-125 + signal \c$ds_app_arg_16\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_33 : Prop_combined_topEntity_types.Tup10; + signal result_34 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_8 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_8 : Prop_combined_topEntity_types.Tup10; + -- Prop2.hs:10:1-43 + signal \c$ds_app_arg_17\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_35 : boolean; + signal \c$case_alt_25\ : signed(1 downto 0); + signal \c$case_alt_26\ : signed(1 downto 0); + signal \c$case_alt_27\ : signed(1 downto 0); + signal \c$case_alt_28\ : signed(1 downto 0); + signal \c$case_alt_29\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_5 : unsigned(4 downto 0); + signal \c$app_arg_14\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_5 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_5 : unsigned(4 downto 0); + signal \c$app_arg_15\ : signed(1 downto 0); + signal result_36 : Prop_combined_topEntity_types.Tup2_1; + -- Prop2.hs:12:1-124 + signal \c$ds_app_arg_18\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_37 : Prop_combined_topEntity_types.Tup10; + signal result_38 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_9 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_9 : Prop_combined_topEntity_types.Tup10; + -- Prop2.hs:8:1-76 + signal \c$ds_app_arg_19\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11) := Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_39 : boolean; + signal \c$app_arg_16\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11); + signal \c$app_arg_17\ : signed(1 downto 0); + signal result_40 : Prop_combined_topEntity_types.Tup2_3; + -- Prop2.hs:16:1-124 + signal \c$ds_app_arg_20\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(11,5) +, Tup10_sel7_unsigned_7 => to_unsigned(11,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(7,5) +, Tup10_sel3_unsigned_3 => to_unsigned(11,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_41 : Prop_combined_topEntity_types.Tup10; + signal result_42 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_10 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_10 : Prop_combined_topEntity_types.Tup10; + -- Prop2.hs:8:1-76 + signal \c$ds_app_arg_21\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11) := Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_43 : boolean; + signal \c$app_arg_18\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11); + signal \c$app_arg_19\ : signed(1 downto 0); + signal result_44 : Prop_combined_topEntity_types.Tup2_3; + -- Prop2.hs:14:1-125 + signal \c$ds_app_arg_22\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_45 : Prop_combined_topEntity_types.Tup10; + signal result_46 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_11 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_11 : Prop_combined_topEntity_types.Tup10; + -- Prop1.hs:8:1-43 + signal \c$ds_app_arg_23\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_47 : boolean; + signal \c$case_alt_30\ : signed(1 downto 0); + signal \c$case_alt_31\ : signed(1 downto 0); + signal \c$case_alt_32\ : signed(1 downto 0); + signal \c$case_alt_33\ : signed(1 downto 0); + signal \c$case_alt_34\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_6 : unsigned(4 downto 0); + signal \c$app_arg_20\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_6 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_6 : unsigned(4 downto 0); + signal \c$app_arg_21\ : signed(1 downto 0); + signal result_48 : Prop_combined_topEntity_types.Tup2_1; + -- Prop1.hs:12:1-124 + signal \c$ds_app_arg_24\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_49 : Prop_combined_topEntity_types.Tup10; + signal result_50 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_12 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_12 : Prop_combined_topEntity_types.Tup10; + -- Prop1.hs:8:1-43 + signal \c$ds_app_arg_25\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_51 : boolean; + signal \c$case_alt_35\ : signed(1 downto 0); + signal \c$case_alt_36\ : signed(1 downto 0); + signal \c$case_alt_37\ : signed(1 downto 0); + signal \c$case_alt_38\ : signed(1 downto 0); + signal \c$case_alt_39\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_7 : unsigned(4 downto 0); + signal \c$app_arg_22\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_7 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_7 : unsigned(4 downto 0); + signal \c$app_arg_23\ : signed(1 downto 0); + signal result_52 : Prop_combined_topEntity_types.Tup2_1; + -- Prop1.hs:14:1-125 + signal \c$ds_app_arg_26\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_53 : Prop_combined_topEntity_types.Tup10; + signal result_54 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_13 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_13 : Prop_combined_topEntity_types.Tup10; + -- Prop1.hs:8:1-43 + signal \c$ds_app_arg_27\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 0) := Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_55 : boolean; + signal \c$case_alt_40\ : signed(1 downto 0); + signal \c$case_alt_41\ : signed(1 downto 0); + signal \c$case_alt_42\ : signed(1 downto 0); + signal \c$case_alt_43\ : signed(1 downto 0); + signal \c$case_alt_44\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_8 : unsigned(4 downto 0); + signal \c$app_arg_24\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_8 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_8 : unsigned(4 downto 0); + signal \c$app_arg_25\ : signed(1 downto 0); + signal result_56 : Prop_combined_topEntity_types.Tup2_1; + -- Prop1.hs:14:1-125 + signal \c$ds_app_arg_28\ : Prop_combined_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_57 : Prop_combined_topEntity_types.Tup10; + signal result_58 : Prop_combined_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_14 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_14 : Prop_combined_topEntity_types.Tup10; + signal eta1 : Prop_combined_topEntity_types.Tup6; + signal \c$tt1_case_alt_selection_res\ : boolean; + signal \c$tt1_case_alt_selection_res_0\ : boolean; + signal \c$tt2_case_alt_selection_res\ : boolean; + signal \c$tt2_case_alt_selection_res_0\ : boolean; + signal \c$ff1_case_alt_selection_res\ : boolean; + signal \c$ff1_case_alt_selection_res_0\ : boolean; + signal \c$ff2_case_alt_selection_res\ : boolean; + signal \c$ff2_case_alt_selection_res_0\ : boolean; + signal \c$mm1_case_alt_selection_res\ : boolean; + signal \c$mm1_case_alt_selection_res_0\ : boolean; + signal \c$mm2_case_alt_selection_res\ : boolean; + signal \c$mm2_case_alt_selection_res_0\ : boolean; + signal \c$tm1_case_alt_selection_res\ : boolean; + signal \c$tm1_case_alt_selection_res_0\ : boolean; + signal \c$tm2_case_alt_selection_res\ : boolean; + signal \c$tm2_case_alt_selection_res_0\ : boolean; + signal \c$fm1_case_alt_selection_res\ : boolean; + signal \c$fm1_case_alt_selection_res_0\ : boolean; + signal \c$fm2_case_alt_selection_res\ : boolean; + signal \c$fm2_case_alt_selection_res_0\ : boolean; + signal \c$vec\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 20); + signal result_0_1 : Prop_combined_topEntity_types.Tup2_4; + signal \c$vec_0\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 19); + signal fm2_selection_res : boolean; + signal fm1_selection_res : boolean; + signal tm2_selection_res : boolean; + signal tm1_selection_res : boolean; + signal mm2_selection_res : boolean; + signal mm1_selection_res : boolean; + signal ff2_selection_res : boolean; + signal ff1_selection_res : boolean; + signal tt2_selection_res : boolean; + signal tt1_selection_res : boolean; + signal ds4_selection_res : boolean; + signal ds4_selection_res_0 : boolean; + signal ds4_selection_res_1 : boolean; + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + signal \c$vec_1\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_19\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_2\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_0_2\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_2 : boolean; + signal \c$vec_3\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 7); + signal \c$app_arg_2_4\ : Prop_combined_topEntity_types.Tup2_6; + signal \c$vec_4\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_3 : boolean; + signal \c$vec_5\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 7); + signal \c$app_arg_4_6\ : Prop_combined_topEntity_types.Tup2_6; + signal \c$vec_6\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_4 : boolean; + signal \c$case_alt_selection_res_19\ : boolean; + signal \c$case_alt_selection_res_20\ : boolean; + signal \c$case_alt_selection_res_21\ : boolean; + signal \c$case_alt_selection_res_22\ : boolean; + signal \c$case_alt_selection_res_23\ : boolean; + signal \c$vec_7\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_51\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_8\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_6_9\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_5 : boolean; + signal \c$case_alt_selection_res_24\ : boolean; + signal \c$case_alt_selection_res_25\ : boolean; + signal \c$case_alt_selection_res_26\ : boolean; + signal \c$case_alt_selection_res_27\ : boolean; + signal \c$case_alt_selection_res_28\ : boolean; + signal \c$vec_9\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_63\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_10\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_8_12\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_6 : boolean; + signal \c$case_alt_selection_res_29\ : boolean; + signal \c$case_alt_selection_res_30\ : boolean; + signal \c$case_alt_selection_res_31\ : boolean; + signal \c$case_alt_selection_res_32\ : boolean; + signal \c$case_alt_selection_res_33\ : boolean; + signal \c$vec_11\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_75\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_12\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_10_15\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_7 : boolean; + signal \c$case_alt_selection_res_34\ : boolean; + signal \c$case_alt_selection_res_35\ : boolean; + signal \c$case_alt_selection_res_36\ : boolean; + signal \c$case_alt_selection_res_37\ : boolean; + signal \c$case_alt_selection_res_38\ : boolean; + signal \c$vec_13\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_87\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_14\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_12_18\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_8 : boolean; + signal \c$case_alt_selection_res_39\ : boolean; + signal \c$case_alt_selection_res_40\ : boolean; + signal \c$case_alt_selection_res_41\ : boolean; + signal \c$case_alt_selection_res_42\ : boolean; + signal \c$case_alt_selection_res_43\ : boolean; + signal \c$vec_15\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_99\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_16\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_14_21\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_9 : boolean; + signal \c$vec_17\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 12); + signal \c$app_arg_16_23\ : Prop_combined_topEntity_types.Tup2_7; + signal \c$vec_18\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_10 : boolean; + signal \c$vec_19\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 12); + signal \c$app_arg_18_25\ : Prop_combined_topEntity_types.Tup2_7; + signal \c$vec_20\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_11 : boolean; + signal \c$case_alt_selection_res_54\ : boolean; + signal \c$case_alt_selection_res_55\ : boolean; + signal \c$case_alt_selection_res_56\ : boolean; + signal \c$case_alt_selection_res_57\ : boolean; + signal \c$case_alt_selection_res_58\ : boolean; + signal \c$vec_21\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_131\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_22\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_20_28\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_12 : boolean; + signal \c$case_alt_selection_res_59\ : boolean; + signal \c$case_alt_selection_res_60\ : boolean; + signal \c$case_alt_selection_res_61\ : boolean; + signal \c$case_alt_selection_res_62\ : boolean; + signal \c$case_alt_selection_res_63\ : boolean; + signal \c$vec_23\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_143\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_24\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_22_31\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_13 : boolean; + signal \c$case_alt_selection_res_64\ : boolean; + signal \c$case_alt_selection_res_65\ : boolean; + signal \c$case_alt_selection_res_66\ : boolean; + signal \c$case_alt_selection_res_67\ : boolean; + signal \c$case_alt_selection_res_68\ : boolean; + signal \c$vec_25\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_155\ : Prop_combined_topEntity_types.Tup2_5; + signal \c$vec_26\ : Prop_combined_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_24_34\ : Prop_combined_topEntity_types.Tup2_5; + signal ds4_selection_res_14 : boolean; + signal ccase_alt : Prop_combined_topEntity_types.Tup5; + +begin + eta1 <= ( Tup6_sel0_boolean_0 => eta1_0 + , Tup6_sel1_boolean_1 => eta1_1 + , Tup6_sel2_boolean_2 => eta1_2 + , Tup6_sel3_boolean_3 => eta1_3 + , Tup6_sel4_boolean_4 => eta1_4 + , Tup6_sel5_boolean_5 => eta1_5 ); + + drain <= eta1.Tup6_sel0_boolean_0; + + dry <= eta1.Tup6_sel1_boolean_1; + + start <= eta1.Tup6_sel2_boolean_2; + + wash <= eta1.Tup6_sel3_boolean_3; + + fill <= eta1.Tup6_sel4_boolean_4; + + soak <= eta1.Tup6_sel5_boolean_5; + + ccase_alt <= ( Tup5_sel0_boolean_0 => result_47 + , Tup5_sel1_boolean_1 => result_35 + , Tup5_sel2_boolean_2 => result_19 + , Tup5_sel3_boolean_3 => result_7 + , Tup5_sel4_boolean_4 => result ); + + -- register begin + cds_app_arg_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg\ <= Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg\ <= \c$case_alt\.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result <= \c$case_alt\.Tup2_sel1_boolean; + + \c$tt1_case_alt_selection_res\ <= tt12 <= tt13; + + \c$tt1_case_alt\ <= tt12 when \c$tt1_case_alt_selection_res\ else + tt13; + + \c$tt1_case_alt_selection_res_0\ <= tt11 <= tt13; + + \c$tt1_case_alt_0\ <= tt11 when \c$tt1_case_alt_selection_res_0\ else + tt13; + + \c$tt2_case_alt_selection_res\ <= tt22 <= tt23; + + \c$tt2_case_alt\ <= tt22 when \c$tt2_case_alt_selection_res\ else + tt23; + + \c$tt2_case_alt_selection_res_0\ <= tt21 <= tt23; + + \c$tt2_case_alt_0\ <= tt21 when \c$tt2_case_alt_selection_res_0\ else + tt23; + + \c$ff1_case_alt_selection_res\ <= ff12 <= ff13; + + \c$ff1_case_alt\ <= ff12 when \c$ff1_case_alt_selection_res\ else + ff13; + + \c$ff1_case_alt_selection_res_0\ <= ff11 <= ff13; + + \c$ff1_case_alt_0\ <= ff11 when \c$ff1_case_alt_selection_res_0\ else + ff13; + + \c$ff2_case_alt_selection_res\ <= ff22 <= ff23; + + \c$ff2_case_alt\ <= ff22 when \c$ff2_case_alt_selection_res\ else + ff23; + + \c$ff2_case_alt_selection_res_0\ <= ff21 <= ff23; + + \c$ff2_case_alt_0\ <= ff21 when \c$ff2_case_alt_selection_res_0\ else + ff23; + + \c$mm1_case_alt_selection_res\ <= mm12 <= mm13; + + \c$mm1_case_alt\ <= mm12 when \c$mm1_case_alt_selection_res\ else + mm13; + + \c$mm1_case_alt_selection_res_0\ <= mm11 <= mm13; + + \c$mm1_case_alt_0\ <= mm11 when \c$mm1_case_alt_selection_res_0\ else + mm13; + + \c$mm2_case_alt_selection_res\ <= mm22 <= mm23; + + \c$mm2_case_alt\ <= mm22 when \c$mm2_case_alt_selection_res\ else + mm23; + + \c$mm2_case_alt_selection_res_0\ <= mm21 <= mm23; + + \c$mm2_case_alt_0\ <= mm21 when \c$mm2_case_alt_selection_res_0\ else + mm23; + + \c$tm1_case_alt_selection_res\ <= tm12 <= tm13; + + \c$tm1_case_alt\ <= tm12 when \c$tm1_case_alt_selection_res\ else + tm13; + + \c$tm1_case_alt_selection_res_0\ <= tm11 <= tm13; + + \c$tm1_case_alt_0\ <= tm11 when \c$tm1_case_alt_selection_res_0\ else + tm13; + + \c$tm2_case_alt_selection_res\ <= tm22 <= tm23; + + \c$tm2_case_alt\ <= tm22 when \c$tm2_case_alt_selection_res\ else + tm23; + + \c$tm2_case_alt_selection_res_0\ <= tm21 <= tm23; + + \c$tm2_case_alt_0\ <= tm21 when \c$tm2_case_alt_selection_res_0\ else + tm23; + + \c$fm1_case_alt_selection_res\ <= fm12 <= fm13; + + \c$fm1_case_alt\ <= fm12 when \c$fm1_case_alt_selection_res\ else + fm13; + + \c$fm1_case_alt_selection_res_0\ <= fm11 <= fm13; + + \c$fm1_case_alt_0\ <= fm11 when \c$fm1_case_alt_selection_res_0\ else + fm13; + + \c$fm2_case_alt_selection_res\ <= fm22 <= fm23; + + \c$fm2_case_alt\ <= fm22 when \c$fm2_case_alt_selection_res\ else + fm23; + + \c$fm2_case_alt_selection_res_0\ <= fm21 <= fm23; + + \c$fm2_case_alt_0\ <= fm21 when \c$fm2_case_alt_selection_res_0\ else + fm23; + + \c$vec\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + result_0_1 <= (\c$vec\(0 to 20-1),\c$vec\(20 to \c$vec\'high)); + + \c$vec_0\ <= result_0_1.Tup2_4_sel0_array_of_signed_2_0; + + -- imap begin + imap : block + function max (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_0 : for i in result_0'range generate + begin + fun_4 : block + signal \c$app_arg_26\ : signed(63 downto 0); + signal \c$case_alt_45\ : signed(1 downto 0); + signal \c$case_alt_46\ : signed(1 downto 0); + signal \c$case_alt_47\ : signed(1 downto 0); + signal \c$case_alt_48\ : signed(1 downto 0); + signal \c$case_alt_49\ : signed(1 downto 0); + signal \c$app_arg_27\ : boolean; + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + begin + result_0(i) <= \c$case_alt_45\; + + \c$app_arg_26\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(20)))))),64))); + + \c$case_alt_selection_res\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) <= tt2) and ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) >= tt1); + + \c$case_alt_45\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_46\; + + \c$case_alt_selection_res_0\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) <= ff2) and ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) >= ff1); + + \c$case_alt_46\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_47\; + + \c$case_alt_selection_res_1\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) <= tm2) and (((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) >= tm1) and \c$app_arg_27\); + + \c$case_alt_47\ <= to_signed(1,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_48\; + + \c$case_alt_selection_res_2\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) <= fm2) and (((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) >= fm1) and \c$app_arg_27\); + + \c$case_alt_48\ <= to_signed(-1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_49\; + + \c$case_alt_selection_res_3\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) <= mm2) and ((resize(unsigned(std_logic_vector(\c$app_arg_26\)),5)) >= mm1); + + \c$case_alt_49\ <= to_signed(0,2) when \c$case_alt_selection_res_3\ else + \c$vec_0\(i); + + \c$app_arg_27\ <= \c$vec_0\(i) = to_signed(0,2); + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 20-1; + begin + vec_index <= to_integer(to_signed(19,64)) + -- pragma translate_off + mod 20 + -- pragma translate_on + ; + \c$app_arg\ <= \c$ds_app_arg\(vec_index); + end block; + -- index end + + \c$case_alt\ <= ( Tup2_sel0_array_of_signed_2 => result_0 + , Tup2_sel1_boolean => \c$app_arg\ = to_signed(1,2) ); + + tt11 <= result_5.Tup10_sel0_unsigned_0; + + tt21 <= result_5.Tup10_sel1_unsigned_1; + + ff11 <= result_5.Tup10_sel2_unsigned_2; + + ff21 <= result_5.Tup10_sel3_unsigned_3; + + mm11 <= result_5.Tup10_sel4_unsigned_4; + + mm21 <= result_5.Tup10_sel5_unsigned_5; + + tm11 <= result_5.Tup10_sel6_unsigned_6; + + tm21 <= result_5.Tup10_sel7_unsigned_7; + + fm11 <= result_5.Tup10_sel8_unsigned_8; + + fm21 <= result_5.Tup10_sel9_unsigned_9; + + tt12 <= result_3.Tup10_sel0_unsigned_0; + + tt22 <= result_3.Tup10_sel1_unsigned_1; + + ff12 <= result_3.Tup10_sel2_unsigned_2; + + ff22 <= result_3.Tup10_sel3_unsigned_3; + + mm12 <= result_3.Tup10_sel4_unsigned_4; + + mm22 <= result_3.Tup10_sel5_unsigned_5; + + tm12 <= result_3.Tup10_sel6_unsigned_6; + + tm22 <= result_3.Tup10_sel7_unsigned_7; + + fm12 <= result_3.Tup10_sel8_unsigned_8; + + fm22 <= result_3.Tup10_sel9_unsigned_9; + + tt13 <= result_1.Tup10_sel0_unsigned_0; + + tt23 <= result_1.Tup10_sel1_unsigned_1; + + ff13 <= result_1.Tup10_sel2_unsigned_2; + + ff23 <= result_1.Tup10_sel3_unsigned_3; + + mm13 <= result_1.Tup10_sel4_unsigned_4; + + mm23 <= result_1.Tup10_sel5_unsigned_5; + + tm13 <= result_1.Tup10_sel6_unsigned_6; + + tm23 <= result_1.Tup10_sel7_unsigned_7; + + fm13 <= result_1.Tup10_sel8_unsigned_8; + + fm23 <= result_1.Tup10_sel9_unsigned_9; + + fm2_selection_res <= fm21 <= fm22; + + fm2 <= \c$fm2_case_alt_0\ when fm2_selection_res else + \c$fm2_case_alt\; + + fm1_selection_res <= fm11 <= fm12; + + fm1 <= \c$fm1_case_alt_0\ when fm1_selection_res else + \c$fm1_case_alt\; + + tm2_selection_res <= tm21 <= tm22; + + tm2 <= \c$tm2_case_alt_0\ when tm2_selection_res else + \c$tm2_case_alt\; + + tm1_selection_res <= tm11 <= tm12; + + tm1 <= \c$tm1_case_alt_0\ when tm1_selection_res else + \c$tm1_case_alt\; + + mm2_selection_res <= mm21 <= mm22; + + mm2 <= \c$mm2_case_alt_0\ when mm2_selection_res else + \c$mm2_case_alt\; + + mm1_selection_res <= mm11 <= mm12; + + mm1 <= \c$mm1_case_alt_0\ when mm1_selection_res else + \c$mm1_case_alt\; + + ff2_selection_res <= ff21 <= ff22; + + ff2 <= \c$ff2_case_alt_0\ when ff2_selection_res else + \c$ff2_case_alt\; + + ff1_selection_res <= ff11 <= ff12; + + ff1 <= \c$ff1_case_alt_0\ when ff1_selection_res else + \c$ff1_case_alt\; + + tt2_selection_res <= tt21 <= tt22; + + tt2 <= \c$tt2_case_alt_0\ when tt2_selection_res else + \c$tt2_case_alt\; + + tt1_selection_res <= tt11 <= tt12; + + tt1 <= \c$tt1_case_alt_0\ when tt1_selection_res else + \c$tt1_case_alt\; + + -- register begin + cds_app_arg_0_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_0\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(0,5) + , Tup10_sel9_unsigned_9 => to_unsigned(19,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_0\ <= result_2.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_1 <= result_2.Tup2_0_sel1_Tup10; + + result_2 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_0\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_0\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (start or dry)) or ((opcode = to_unsigned(1,1)) and start); + + ds4 <= \c$ds_app_arg_0\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_0\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_1_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_1\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(0,5) + , Tup10_sel7_unsigned_7 => to_unsigned(19,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(19,5) + , Tup10_sel9_unsigned_9 => to_unsigned(19,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_1\ <= result_4.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_3 <= result_4.Tup2_0_sel1_Tup10; + + result_4 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_1\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_1\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (dry or dry)) or ((opcode_0 = to_unsigned(1,1)) and dry); + + ds4_0 <= \c$ds_app_arg_1\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_1\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_2_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_2\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_2\ <= result_6.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_5 <= result_6.Tup2_0_sel1_Tup10; + + result_6 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_2\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_2\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (start or start)) or ((opcode_1 = to_unsigned(1,1)) and start); + + ds4_1 <= \c$ds_app_arg_2\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_2\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_3_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_3\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_3\ <= result_8.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_7 <= result_8.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_4\ <= (to_unsigned(0,5) <= tt2_0) and (to_unsigned(0,5) >= tt1_0); + + \c$case_alt_0\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_5\ <= (to_unsigned(0,5) <= ff2_0) and (to_unsigned(0,5) >= ff1_0); + + \c$case_alt_1\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_6\ <= (to_unsigned(0,5) <= mm2_0) and (to_unsigned(0,5) >= mm1_0); + + \c$case_alt_2\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_7\ <= (to_unsigned(0,5) <= tm2_0) and ((to_unsigned(0,5) >= tm1_0) and \c$app_arg_0\); + + \c$case_alt_3\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_4\; + + \c$case_alt_selection_res_8\ <= (to_unsigned(0,5) <= fm2_0) and ((to_unsigned(0,5) >= fm1_0) and \c$app_arg_0\); + + \c$vec_1\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$case_alt_sel_alt_19\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_4\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$case_alt_sel_alt_19\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_0 <= result_9.Tup10_sel8_unsigned_8; + + fm2_0 <= result_9.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$app_arg_0_2\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg_0\ <= \c$app_arg_0_2\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_0 <= result_9.Tup10_sel6_unsigned_6; + + tm2_0 <= result_9.Tup10_sel7_unsigned_7; + + mm1_0 <= result_9.Tup10_sel4_unsigned_4; + + mm2_0 <= result_9.Tup10_sel5_unsigned_5; + + ff1_0 <= result_9.Tup10_sel2_unsigned_2; + + ff2_0 <= result_9.Tup10_sel3_unsigned_3; + + tt1_0 <= result_9.Tup10_sel0_unsigned_0; + + tt2_0 <= result_9.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 1-1; + begin + vec_index_0 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_1\ <= \c$ds_app_arg_3\(vec_index_0); + end block; + -- index end + + result_8 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_0\) + , Tup2_1_sel1_boolean => \c$app_arg_1\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_4_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_4\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_4\ <= result_10.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_9 <= result_10.Tup2_0_sel1_Tup10; + + result_10 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_4\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_2.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_2.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_2.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_2.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_2.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_2.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_2.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_2.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_2.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_2.Tup10_sel9_unsigned_9 ) ); + + opcode_2 <= \c$ds_app_arg_4\.Tup3_sel0_unsigned; + + ds4_selection_res_2 <= ((opcode_2 = to_unsigned(0,1)) and (result_15 or result_11)) or ((opcode_2 = to_unsigned(1,1)) and result_15); + + ds4_2 <= \c$ds_app_arg_4\.Tup3_sel1_Tup10_0 when ds4_selection_res_2 else + \c$ds_app_arg_4\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_5_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_5\ <= Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_5\ <= result_12.Tup2_2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_11 <= result_12.Tup2_2_sel1_boolean; + + \c$vec_3\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_5\))); + + \c$app_arg_2_4\ <= (\c$vec_3\(0 to 7-1),\c$vec_3\(7 to \c$vec_3\'high)); + + \c$vec_4\ <= \c$app_arg_2_4\.Tup2_6_sel0_array_of_signed_2_0; + + -- imap begin + imap_1 : block + function max_0 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_2 : for i_0 in \c$app_arg_2\'range generate + begin + fun_5 : block + signal \c$app_arg_28\ : signed(63 downto 0); + signal \c$case_alt_51\ : signed(1 downto 0); + signal \c$case_alt_52\ : signed(1 downto 0); + signal \c$case_alt_53\ : signed(1 downto 0); + signal \c$case_alt_54\ : signed(1 downto 0); + signal \c$case_alt_55\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_12 : unsigned(4 downto 0); + signal \c$app_arg_29\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_12 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_12 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + begin + \c$app_arg_2\(i_0) <= \c$case_alt_51\; + + \c$app_arg_28\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) <= tt2_12) and ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) >= tt1_12); + + \c$case_alt_51\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_52\; + + \c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) <= ff2_12) and ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) >= ff1_12); + + \c$case_alt_52\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_53\; + + \c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) <= mm2_12) and ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) >= mm1_12); + + \c$case_alt_53\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_54\; + + \c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) <= tm2_12) and (((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) >= tm1_12) and \c$app_arg_29\); + + \c$case_alt_54\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_55\; + + \c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) <= fm2_12) and (((resize(unsigned(std_logic_vector(\c$app_arg_28\)),5)) >= fm1_12) and \c$app_arg_29\); + + \c$case_alt_55\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$vec_4\(i_0); + + fm1_12 <= result_13.Tup10_sel8_unsigned_8; + + fm2_12 <= result_13.Tup10_sel9_unsigned_9; + + \c$app_arg_29\ <= \c$vec_4\(i_0) = to_signed(0,2); + + tm1_12 <= result_13.Tup10_sel6_unsigned_6; + + tm2_12 <= result_13.Tup10_sel7_unsigned_7; + + mm1_12 <= result_13.Tup10_sel4_unsigned_4; + + mm2_12 <= result_13.Tup10_sel5_unsigned_5; + + ff1_12 <= result_13.Tup10_sel2_unsigned_2; + + ff2_12 <= result_13.Tup10_sel3_unsigned_3; + + tt1_12 <= result_13.Tup10_sel0_unsigned_0; + + tt2_12 <= result_13.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 7-1; + begin + vec_index_1 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_3\ <= \c$ds_app_arg_5\(vec_index_1); + end block; + -- index end + + result_12 <= ( Tup2_2_sel0_array_of_signed_2 => \c$app_arg_2\ + , Tup2_2_sel1_boolean => \c$app_arg_3\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_6_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_6\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) + , Tup10_sel1_unsigned_1 => to_unsigned(6,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(6,5) + , Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_6\ <= result_14.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_13 <= result_14.Tup2_0_sel1_Tup10; + + result_14 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_6\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_3.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_3.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_3.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_3.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_3.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_3.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_3.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_3.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_3.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_3.Tup10_sel9_unsigned_9 ) ); + + opcode_3 <= \c$ds_app_arg_6\.Tup3_sel0_unsigned; + + ds4_selection_res_3 <= ((opcode_3 = to_unsigned(0,1)) and (soak or soak)) or ((opcode_3 = to_unsigned(1,1)) and soak); + + ds4_3 <= \c$ds_app_arg_6\.Tup3_sel1_Tup10_0 when ds4_selection_res_3 else + \c$ds_app_arg_6\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_7_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_7\ <= Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_7\ <= result_16.Tup2_2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_15 <= result_16.Tup2_2_sel1_boolean; + + \c$vec_5\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_7\))); + + \c$app_arg_4_6\ <= (\c$vec_5\(0 to 7-1),\c$vec_5\(7 to \c$vec_5\'high)); + + \c$vec_6\ <= \c$app_arg_4_6\.Tup2_6_sel0_array_of_signed_2_0; + + -- imap begin + imap_3 : block + function max_1 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_4 : for i_1 in \c$app_arg_4\'range generate + begin + fun_6 : block + signal \c$app_arg_30\ : signed(63 downto 0); + signal \c$case_alt_56\ : signed(1 downto 0); + signal \c$case_alt_57\ : signed(1 downto 0); + signal \c$case_alt_58\ : signed(1 downto 0); + signal \c$case_alt_59\ : signed(1 downto 0); + signal \c$case_alt_60\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_13 : unsigned(4 downto 0); + signal \c$app_arg_31\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_13 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_13 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_14\ : boolean; + signal \c$case_alt_selection_res_15\ : boolean; + signal \c$case_alt_selection_res_16\ : boolean; + signal \c$case_alt_selection_res_17\ : boolean; + signal \c$case_alt_selection_res_18\ : boolean; + begin + \c$app_arg_4\(i_1) <= \c$case_alt_56\; + + \c$app_arg_30\ <= signed(std_logic_vector(resize(to_unsigned(i_1,max_1(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_14\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) <= tt2_13) and ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) >= tt1_13); + + \c$case_alt_56\ <= to_signed(1,2) when \c$case_alt_selection_res_14\ else + \c$case_alt_57\; + + \c$case_alt_selection_res_15\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) <= ff2_13) and ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) >= ff1_13); + + \c$case_alt_57\ <= to_signed(-1,2) when \c$case_alt_selection_res_15\ else + \c$case_alt_58\; + + \c$case_alt_selection_res_16\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) <= mm2_13) and ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) >= mm1_13); + + \c$case_alt_58\ <= to_signed(0,2) when \c$case_alt_selection_res_16\ else + \c$case_alt_59\; + + \c$case_alt_selection_res_17\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) <= tm2_13) and (((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) >= tm1_13) and \c$app_arg_31\); + + \c$case_alt_59\ <= to_signed(1,2) when \c$case_alt_selection_res_17\ else + \c$case_alt_60\; + + \c$case_alt_selection_res_18\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) <= fm2_13) and (((resize(unsigned(std_logic_vector(\c$app_arg_30\)),5)) >= fm1_13) and \c$app_arg_31\); + + \c$case_alt_60\ <= to_signed(-1,2) when \c$case_alt_selection_res_18\ else + \c$vec_6\(i_1); + + fm1_13 <= result_17.Tup10_sel8_unsigned_8; + + fm2_13 <= result_17.Tup10_sel9_unsigned_9; + + \c$app_arg_31\ <= \c$vec_6\(i_1) = to_signed(0,2); + + tm1_13 <= result_17.Tup10_sel6_unsigned_6; + + tm2_13 <= result_17.Tup10_sel7_unsigned_7; + + mm1_13 <= result_17.Tup10_sel4_unsigned_4; + + mm2_13 <= result_17.Tup10_sel5_unsigned_5; + + ff1_13 <= result_17.Tup10_sel2_unsigned_2; + + ff2_13 <= result_17.Tup10_sel3_unsigned_3; + + tt1_13 <= result_17.Tup10_sel0_unsigned_0; + + tt2_13 <= result_17.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 7-1; + begin + vec_index_2 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_5\ <= \c$ds_app_arg_7\(vec_index_2); + end block; + -- index end + + result_16 <= ( Tup2_2_sel0_array_of_signed_2 => \c$app_arg_4\ + , Tup2_2_sel1_boolean => \c$app_arg_5\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_8_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_8\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_8\ <= result_18.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_17 <= result_18.Tup2_0_sel1_Tup10; + + result_18 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_8\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_4.Tup10_sel9_unsigned_9 ) ); + + opcode_4 <= \c$ds_app_arg_8\.Tup3_sel0_unsigned; + + ds4_selection_res_4 <= ((opcode_4 = to_unsigned(0,1)) and (start or start)) or ((opcode_4 = to_unsigned(1,1)) and start); + + ds4_4 <= \c$ds_app_arg_8\.Tup3_sel1_Tup10_0 when ds4_selection_res_4 else + \c$ds_app_arg_8\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_9_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_9\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_9\ <= result_20.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_19 <= result_20.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_19\ <= (to_unsigned(0,5) <= tt2_1) and (to_unsigned(0,5) >= tt1_1); + + \c$case_alt_5\ <= to_signed(1,2) when \c$case_alt_selection_res_19\ else + \c$case_alt_6\; + + \c$case_alt_selection_res_20\ <= (to_unsigned(0,5) <= ff2_1) and (to_unsigned(0,5) >= ff1_1); + + \c$case_alt_6\ <= to_signed(-1,2) when \c$case_alt_selection_res_20\ else + \c$case_alt_7\; + + \c$case_alt_selection_res_21\ <= (to_unsigned(0,5) <= mm2_1) and (to_unsigned(0,5) >= mm1_1); + + \c$case_alt_7\ <= to_signed(0,2) when \c$case_alt_selection_res_21\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_22\ <= (to_unsigned(0,5) <= tm2_1) and ((to_unsigned(0,5) >= tm1_1) and \c$app_arg_6\); + + \c$case_alt_8\ <= to_signed(1,2) when \c$case_alt_selection_res_22\ else + \c$case_alt_9\; + + \c$case_alt_selection_res_23\ <= (to_unsigned(0,5) <= fm2_1) and ((to_unsigned(0,5) >= fm1_1) and \c$app_arg_6\); + + \c$vec_7\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_9\))); + + \c$case_alt_sel_alt_51\ <= (\c$vec_7\(0 to 1-1),\c$vec_7\(1 to \c$vec_7\'high)); + + \c$case_alt_9\ <= to_signed(-1,2) when \c$case_alt_selection_res_23\ else + \c$case_alt_sel_alt_51\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_1 <= result_21.Tup10_sel8_unsigned_8; + + fm2_1 <= result_21.Tup10_sel9_unsigned_9; + + \c$vec_8\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_9\))); + + \c$app_arg_6_9\ <= (\c$vec_8\(0 to 1-1),\c$vec_8\(1 to \c$vec_8\'high)); + + \c$app_arg_6\ <= \c$app_arg_6_9\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_1 <= result_21.Tup10_sel6_unsigned_6; + + tm2_1 <= result_21.Tup10_sel7_unsigned_7; + + mm1_1 <= result_21.Tup10_sel4_unsigned_4; + + mm2_1 <= result_21.Tup10_sel5_unsigned_5; + + ff1_1 <= result_21.Tup10_sel2_unsigned_2; + + ff2_1 <= result_21.Tup10_sel3_unsigned_3; + + tt1_1 <= result_21.Tup10_sel0_unsigned_0; + + tt2_1 <= result_21.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_3 : block + signal vec_index_3 : integer range 0 to 1-1; + begin + vec_index_3 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_7\ <= \c$ds_app_arg_9\(vec_index_3); + end block; + -- index end + + result_20 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_5\) + , Tup2_1_sel1_boolean => \c$app_arg_7\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_10_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_10\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_10\ <= result_22.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_21 <= result_22.Tup2_0_sel1_Tup10; + + result_22 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_10\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_5.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_5.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_5.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_5.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_5.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_5.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_5.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_5.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_5.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_5.Tup10_sel9_unsigned_9 ) ); + + opcode_5 <= \c$ds_app_arg_10\.Tup3_sel0_unsigned; + + ds4_selection_res_5 <= ((opcode_5 = to_unsigned(0,1)) and (result_31 or result_23)) or ((opcode_5 = to_unsigned(1,1)) and result_31); + + ds4_5 <= \c$ds_app_arg_10\.Tup3_sel1_Tup10_0 when ds4_selection_res_5 else + \c$ds_app_arg_10\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_11_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_11\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_11\ <= result_24.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_23 <= result_24.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_24\ <= (to_unsigned(0,5) <= tt2_2) and (to_unsigned(0,5) >= tt1_2); + + \c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_24\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_25\ <= (to_unsigned(0,5) <= ff2_2) and (to_unsigned(0,5) >= ff1_2); + + \c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_25\ else + \c$case_alt_12\; + + \c$case_alt_selection_res_26\ <= (to_unsigned(0,5) <= mm2_2) and (to_unsigned(0,5) >= mm1_2); + + \c$case_alt_12\ <= to_signed(0,2) when \c$case_alt_selection_res_26\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_27\ <= (to_unsigned(0,5) <= tm2_2) and ((to_unsigned(0,5) >= tm1_2) and \c$app_arg_8\); + + \c$case_alt_13\ <= to_signed(1,2) when \c$case_alt_selection_res_27\ else + \c$case_alt_14\; + + \c$case_alt_selection_res_28\ <= (to_unsigned(0,5) <= fm2_2) and ((to_unsigned(0,5) >= fm1_2) and \c$app_arg_8\); + + \c$vec_9\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_11\))); + + \c$case_alt_sel_alt_63\ <= (\c$vec_9\(0 to 1-1),\c$vec_9\(1 to \c$vec_9\'high)); + + \c$case_alt_14\ <= to_signed(-1,2) when \c$case_alt_selection_res_28\ else + \c$case_alt_sel_alt_63\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_2 <= result_25.Tup10_sel8_unsigned_8; + + fm2_2 <= result_25.Tup10_sel9_unsigned_9; + + \c$vec_10\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_11\))); + + \c$app_arg_8_12\ <= (\c$vec_10\(0 to 1-1),\c$vec_10\(1 to \c$vec_10\'high)); + + \c$app_arg_8\ <= \c$app_arg_8_12\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_2 <= result_25.Tup10_sel6_unsigned_6; + + tm2_2 <= result_25.Tup10_sel7_unsigned_7; + + mm1_2 <= result_25.Tup10_sel4_unsigned_4; + + mm2_2 <= result_25.Tup10_sel5_unsigned_5; + + ff1_2 <= result_25.Tup10_sel2_unsigned_2; + + ff2_2 <= result_25.Tup10_sel3_unsigned_3; + + tt1_2 <= result_25.Tup10_sel0_unsigned_0; + + tt2_2 <= result_25.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_4 : block + signal vec_index_4 : integer range 0 to 1-1; + begin + vec_index_4 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_9\ <= \c$ds_app_arg_11\(vec_index_4); + end block; + -- index end + + result_24 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_10\) + , Tup2_1_sel1_boolean => \c$app_arg_9\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_12_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_12\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) + , Tup10_sel1_unsigned_1 => to_unsigned(1,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(1,5) + , Tup10_sel3_unsigned_3 => to_unsigned(1,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_12\ <= result_26.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_25 <= result_26.Tup2_0_sel1_Tup10; + + result_26 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_12\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_6.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_6.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_6.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_6.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_6.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_6.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_6.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_6.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_6.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_6.Tup10_sel9_unsigned_9 ) ); + + opcode_6 <= \c$ds_app_arg_12\.Tup3_sel0_unsigned; + + ds4_selection_res_6 <= ((opcode_6 = to_unsigned(0,1)) and (result_27 or result_27)) or ((opcode_6 = to_unsigned(1,1)) and result_27); + + ds4_6 <= \c$ds_app_arg_12\.Tup3_sel1_Tup10_0 when ds4_selection_res_6 else + \c$ds_app_arg_12\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_13_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_13\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_13\ <= result_28.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_27 <= result_28.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_29\ <= (to_unsigned(0,5) <= tt2_3) and (to_unsigned(0,5) >= tt1_3); + + \c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_29\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_30\ <= (to_unsigned(0,5) <= ff2_3) and (to_unsigned(0,5) >= ff1_3); + + \c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_30\ else + \c$case_alt_17\; + + \c$case_alt_selection_res_31\ <= (to_unsigned(0,5) <= mm2_3) and (to_unsigned(0,5) >= mm1_3); + + \c$case_alt_17\ <= to_signed(0,2) when \c$case_alt_selection_res_31\ else + \c$case_alt_18\; + + \c$case_alt_selection_res_32\ <= (to_unsigned(0,5) <= tm2_3) and ((to_unsigned(0,5) >= tm1_3) and \c$app_arg_10\); + + \c$case_alt_18\ <= to_signed(1,2) when \c$case_alt_selection_res_32\ else + \c$case_alt_19\; + + \c$case_alt_selection_res_33\ <= (to_unsigned(0,5) <= fm2_3) and ((to_unsigned(0,5) >= fm1_3) and \c$app_arg_10\); + + \c$vec_11\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_13\))); + + \c$case_alt_sel_alt_75\ <= (\c$vec_11\(0 to 1-1),\c$vec_11\(1 to \c$vec_11\'high)); + + \c$case_alt_19\ <= to_signed(-1,2) when \c$case_alt_selection_res_33\ else + \c$case_alt_sel_alt_75\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_3 <= result_29.Tup10_sel8_unsigned_8; + + fm2_3 <= result_29.Tup10_sel9_unsigned_9; + + \c$vec_12\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_13\))); + + \c$app_arg_10_15\ <= (\c$vec_12\(0 to 1-1),\c$vec_12\(1 to \c$vec_12\'high)); + + \c$app_arg_10\ <= \c$app_arg_10_15\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_3 <= result_29.Tup10_sel6_unsigned_6; + + tm2_3 <= result_29.Tup10_sel7_unsigned_7; + + mm1_3 <= result_29.Tup10_sel4_unsigned_4; + + mm2_3 <= result_29.Tup10_sel5_unsigned_5; + + ff1_3 <= result_29.Tup10_sel2_unsigned_2; + + ff2_3 <= result_29.Tup10_sel3_unsigned_3; + + tt1_3 <= result_29.Tup10_sel0_unsigned_0; + + tt2_3 <= result_29.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_5 : block + signal vec_index_5 : integer range 0 to 1-1; + begin + vec_index_5 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_11\ <= \c$ds_app_arg_13\(vec_index_5); + end block; + -- index end + + result_28 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_15\) + , Tup2_1_sel1_boolean => \c$app_arg_11\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_14_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_14\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_14\ <= result_30.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_29 <= result_30.Tup2_0_sel1_Tup10; + + result_30 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_14\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_7.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_7.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_7.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_7.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_7.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_7.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_7.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_7.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_7.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_7.Tup10_sel9_unsigned_9 ) ); + + opcode_7 <= \c$ds_app_arg_14\.Tup3_sel0_unsigned; + + ds4_selection_res_7 <= ((opcode_7 = to_unsigned(0,1)) and (fill or soak)) or ((opcode_7 = to_unsigned(1,1)) and fill); + + ds4_7 <= \c$ds_app_arg_14\.Tup3_sel1_Tup10_0 when ds4_selection_res_7 else + \c$ds_app_arg_14\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_15_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_15\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_15\ <= result_32.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_31 <= result_32.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_34\ <= (to_unsigned(0,5) <= tt2_4) and (to_unsigned(0,5) >= tt1_4); + + \c$case_alt_20\ <= to_signed(1,2) when \c$case_alt_selection_res_34\ else + \c$case_alt_21\; + + \c$case_alt_selection_res_35\ <= (to_unsigned(0,5) <= ff2_4) and (to_unsigned(0,5) >= ff1_4); + + \c$case_alt_21\ <= to_signed(-1,2) when \c$case_alt_selection_res_35\ else + \c$case_alt_22\; + + \c$case_alt_selection_res_36\ <= (to_unsigned(0,5) <= mm2_4) and (to_unsigned(0,5) >= mm1_4); + + \c$case_alt_22\ <= to_signed(0,2) when \c$case_alt_selection_res_36\ else + \c$case_alt_23\; + + \c$case_alt_selection_res_37\ <= (to_unsigned(0,5) <= tm2_4) and ((to_unsigned(0,5) >= tm1_4) and \c$app_arg_12\); + + \c$case_alt_23\ <= to_signed(1,2) when \c$case_alt_selection_res_37\ else + \c$case_alt_24\; + + \c$case_alt_selection_res_38\ <= (to_unsigned(0,5) <= fm2_4) and ((to_unsigned(0,5) >= fm1_4) and \c$app_arg_12\); + + \c$vec_13\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_15\))); + + \c$case_alt_sel_alt_87\ <= (\c$vec_13\(0 to 1-1),\c$vec_13\(1 to \c$vec_13\'high)); + + \c$case_alt_24\ <= to_signed(-1,2) when \c$case_alt_selection_res_38\ else + \c$case_alt_sel_alt_87\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_4 <= result_33.Tup10_sel8_unsigned_8; + + fm2_4 <= result_33.Tup10_sel9_unsigned_9; + + \c$vec_14\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_15\))); + + \c$app_arg_12_18\ <= (\c$vec_14\(0 to 1-1),\c$vec_14\(1 to \c$vec_14\'high)); + + \c$app_arg_12\ <= \c$app_arg_12_18\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_4 <= result_33.Tup10_sel6_unsigned_6; + + tm2_4 <= result_33.Tup10_sel7_unsigned_7; + + mm1_4 <= result_33.Tup10_sel4_unsigned_4; + + mm2_4 <= result_33.Tup10_sel5_unsigned_5; + + ff1_4 <= result_33.Tup10_sel2_unsigned_2; + + ff2_4 <= result_33.Tup10_sel3_unsigned_3; + + tt1_4 <= result_33.Tup10_sel0_unsigned_0; + + tt2_4 <= result_33.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_6 : block + signal vec_index_6 : integer range 0 to 1-1; + begin + vec_index_6 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_13\ <= \c$ds_app_arg_15\(vec_index_6); + end block; + -- index end + + result_32 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_20\) + , Tup2_1_sel1_boolean => \c$app_arg_13\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_16_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_16\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_16\ <= result_34.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_33 <= result_34.Tup2_0_sel1_Tup10; + + result_34 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_16\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_8.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_8.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_8.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_8.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_8.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_8.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_8.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_8.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_8.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_8.Tup10_sel9_unsigned_9 ) ); + + opcode_8 <= \c$ds_app_arg_16\.Tup3_sel0_unsigned; + + ds4_selection_res_8 <= ((opcode_8 = to_unsigned(0,1)) and (fill or fill)) or ((opcode_8 = to_unsigned(1,1)) and fill); + + ds4_8 <= \c$ds_app_arg_16\.Tup3_sel1_Tup10_0 when ds4_selection_res_8 else + \c$ds_app_arg_16\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_17_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_17\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_17\ <= result_36.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_35 <= result_36.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_39\ <= (to_unsigned(0,5) <= tt2_5) and (to_unsigned(0,5) >= tt1_5); + + \c$case_alt_25\ <= to_signed(1,2) when \c$case_alt_selection_res_39\ else + \c$case_alt_26\; + + \c$case_alt_selection_res_40\ <= (to_unsigned(0,5) <= ff2_5) and (to_unsigned(0,5) >= ff1_5); + + \c$case_alt_26\ <= to_signed(-1,2) when \c$case_alt_selection_res_40\ else + \c$case_alt_27\; + + \c$case_alt_selection_res_41\ <= (to_unsigned(0,5) <= mm2_5) and (to_unsigned(0,5) >= mm1_5); + + \c$case_alt_27\ <= to_signed(0,2) when \c$case_alt_selection_res_41\ else + \c$case_alt_28\; + + \c$case_alt_selection_res_42\ <= (to_unsigned(0,5) <= tm2_5) and ((to_unsigned(0,5) >= tm1_5) and \c$app_arg_14\); + + \c$case_alt_28\ <= to_signed(1,2) when \c$case_alt_selection_res_42\ else + \c$case_alt_29\; + + \c$case_alt_selection_res_43\ <= (to_unsigned(0,5) <= fm2_5) and ((to_unsigned(0,5) >= fm1_5) and \c$app_arg_14\); + + \c$vec_15\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_17\))); + + \c$case_alt_sel_alt_99\ <= (\c$vec_15\(0 to 1-1),\c$vec_15\(1 to \c$vec_15\'high)); + + \c$case_alt_29\ <= to_signed(-1,2) when \c$case_alt_selection_res_43\ else + \c$case_alt_sel_alt_99\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_5 <= result_37.Tup10_sel8_unsigned_8; + + fm2_5 <= result_37.Tup10_sel9_unsigned_9; + + \c$vec_16\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_17\))); + + \c$app_arg_14_21\ <= (\c$vec_16\(0 to 1-1),\c$vec_16\(1 to \c$vec_16\'high)); + + \c$app_arg_14\ <= \c$app_arg_14_21\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_5 <= result_37.Tup10_sel6_unsigned_6; + + tm2_5 <= result_37.Tup10_sel7_unsigned_7; + + mm1_5 <= result_37.Tup10_sel4_unsigned_4; + + mm2_5 <= result_37.Tup10_sel5_unsigned_5; + + ff1_5 <= result_37.Tup10_sel2_unsigned_2; + + ff2_5 <= result_37.Tup10_sel3_unsigned_3; + + tt1_5 <= result_37.Tup10_sel0_unsigned_0; + + tt2_5 <= result_37.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_7 : block + signal vec_index_7 : integer range 0 to 1-1; + begin + vec_index_7 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_15\ <= \c$ds_app_arg_17\(vec_index_7); + end block; + -- index end + + result_36 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_25\) + , Tup2_1_sel1_boolean => \c$app_arg_15\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_18_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_18\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_18\ <= result_38.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_37 <= result_38.Tup2_0_sel1_Tup10; + + result_38 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_18\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_9.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_9.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_9.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_9.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_9.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_9.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_9.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_9.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_9.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_9.Tup10_sel9_unsigned_9 ) ); + + opcode_9 <= \c$ds_app_arg_18\.Tup3_sel0_unsigned; + + ds4_selection_res_9 <= ((opcode_9 = to_unsigned(0,1)) and (result_43 or result_39)) or ((opcode_9 = to_unsigned(1,1)) and result_43); + + ds4_9 <= \c$ds_app_arg_18\.Tup3_sel1_Tup10_0 when ds4_selection_res_9 else + \c$ds_app_arg_18\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_19_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_19\ <= Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_19\ <= result_40.Tup2_3_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_39 <= result_40.Tup2_3_sel1_boolean; + + \c$vec_17\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_19\))); + + \c$app_arg_16_23\ <= (\c$vec_17\(0 to 12-1),\c$vec_17\(12 to \c$vec_17\'high)); + + \c$vec_18\ <= \c$app_arg_16_23\.Tup2_7_sel0_array_of_signed_2_0; + + -- imap begin + imap_5 : block + function max_2 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_6 : for i_2 in \c$app_arg_16\'range generate + begin + fun_7 : block + signal \c$app_arg_32\ : signed(63 downto 0); + signal \c$case_alt_61\ : signed(1 downto 0); + signal \c$case_alt_62\ : signed(1 downto 0); + signal \c$case_alt_63\ : signed(1 downto 0); + signal \c$case_alt_64\ : signed(1 downto 0); + signal \c$case_alt_65\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_14 : unsigned(4 downto 0); + signal \c$app_arg_33\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_14 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_14 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_44\ : boolean; + signal \c$case_alt_selection_res_45\ : boolean; + signal \c$case_alt_selection_res_46\ : boolean; + signal \c$case_alt_selection_res_47\ : boolean; + signal \c$case_alt_selection_res_48\ : boolean; + begin + \c$app_arg_16\(i_2) <= \c$case_alt_61\; + + \c$app_arg_32\ <= signed(std_logic_vector(resize(to_unsigned(i_2,max_2(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_44\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) <= tt2_14) and ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) >= tt1_14); + + \c$case_alt_61\ <= to_signed(1,2) when \c$case_alt_selection_res_44\ else + \c$case_alt_62\; + + \c$case_alt_selection_res_45\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) <= ff2_14) and ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) >= ff1_14); + + \c$case_alt_62\ <= to_signed(-1,2) when \c$case_alt_selection_res_45\ else + \c$case_alt_63\; + + \c$case_alt_selection_res_46\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) <= mm2_14) and ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) >= mm1_14); + + \c$case_alt_63\ <= to_signed(0,2) when \c$case_alt_selection_res_46\ else + \c$case_alt_64\; + + \c$case_alt_selection_res_47\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) <= tm2_14) and (((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) >= tm1_14) and \c$app_arg_33\); + + \c$case_alt_64\ <= to_signed(1,2) when \c$case_alt_selection_res_47\ else + \c$case_alt_65\; + + \c$case_alt_selection_res_48\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) <= fm2_14) and (((resize(unsigned(std_logic_vector(\c$app_arg_32\)),5)) >= fm1_14) and \c$app_arg_33\); + + \c$case_alt_65\ <= to_signed(-1,2) when \c$case_alt_selection_res_48\ else + \c$vec_18\(i_2); + + fm1_14 <= result_41.Tup10_sel8_unsigned_8; + + fm2_14 <= result_41.Tup10_sel9_unsigned_9; + + \c$app_arg_33\ <= \c$vec_18\(i_2) = to_signed(0,2); + + tm1_14 <= result_41.Tup10_sel6_unsigned_6; + + tm2_14 <= result_41.Tup10_sel7_unsigned_7; + + mm1_14 <= result_41.Tup10_sel4_unsigned_4; + + mm2_14 <= result_41.Tup10_sel5_unsigned_5; + + ff1_14 <= result_41.Tup10_sel2_unsigned_2; + + ff2_14 <= result_41.Tup10_sel3_unsigned_3; + + tt1_14 <= result_41.Tup10_sel0_unsigned_0; + + tt2_14 <= result_41.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_8 : block + signal vec_index_8 : integer range 0 to 12-1; + begin + vec_index_8 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_17\ <= \c$ds_app_arg_19\(vec_index_8); + end block; + -- index end + + result_40 <= ( Tup2_3_sel0_array_of_signed_2 => \c$app_arg_16\ + , Tup2_3_sel1_boolean => \c$app_arg_17\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_20_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_20\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(11,5) + , Tup10_sel7_unsigned_7 => to_unsigned(11,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(7,5) + , Tup10_sel3_unsigned_3 => to_unsigned(11,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_20\ <= result_42.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_41 <= result_42.Tup2_0_sel1_Tup10; + + result_42 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_20\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_10.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_10.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_10.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_10.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_10.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_10.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_10.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_10.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_10.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_10.Tup10_sel9_unsigned_9 ) ); + + opcode_10 <= \c$ds_app_arg_20\.Tup3_sel0_unsigned; + + ds4_selection_res_10 <= ((opcode_10 = to_unsigned(0,1)) and (wash or wash)) or ((opcode_10 = to_unsigned(1,1)) and wash); + + ds4_10 <= \c$ds_app_arg_20\.Tup3_sel1_Tup10_0 when ds4_selection_res_10 else + \c$ds_app_arg_20\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_21_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_21\ <= Prop_combined_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_21\ <= result_44.Tup2_3_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_43 <= result_44.Tup2_3_sel1_boolean; + + \c$vec_19\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_21\))); + + \c$app_arg_18_25\ <= (\c$vec_19\(0 to 12-1),\c$vec_19\(12 to \c$vec_19\'high)); + + \c$vec_20\ <= \c$app_arg_18_25\.Tup2_7_sel0_array_of_signed_2_0; + + -- imap begin + imap_7 : block + function max_3 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_8 : for i_3 in \c$app_arg_18\'range generate + begin + fun_8 : block + signal \c$app_arg_34\ : signed(63 downto 0); + signal \c$case_alt_66\ : signed(1 downto 0); + signal \c$case_alt_67\ : signed(1 downto 0); + signal \c$case_alt_68\ : signed(1 downto 0); + signal \c$case_alt_69\ : signed(1 downto 0); + signal \c$case_alt_70\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_15 : unsigned(4 downto 0); + signal \c$app_arg_35\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_15 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_15 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_49\ : boolean; + signal \c$case_alt_selection_res_50\ : boolean; + signal \c$case_alt_selection_res_51\ : boolean; + signal \c$case_alt_selection_res_52\ : boolean; + signal \c$case_alt_selection_res_53\ : boolean; + begin + \c$app_arg_18\(i_3) <= \c$case_alt_66\; + + \c$app_arg_34\ <= signed(std_logic_vector(resize(to_unsigned(i_3,max_3(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_49\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) <= tt2_15) and ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) >= tt1_15); + + \c$case_alt_66\ <= to_signed(1,2) when \c$case_alt_selection_res_49\ else + \c$case_alt_67\; + + \c$case_alt_selection_res_50\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) <= ff2_15) and ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) >= ff1_15); + + \c$case_alt_67\ <= to_signed(-1,2) when \c$case_alt_selection_res_50\ else + \c$case_alt_68\; + + \c$case_alt_selection_res_51\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) <= mm2_15) and ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) >= mm1_15); + + \c$case_alt_68\ <= to_signed(0,2) when \c$case_alt_selection_res_51\ else + \c$case_alt_69\; + + \c$case_alt_selection_res_52\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) <= tm2_15) and (((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) >= tm1_15) and \c$app_arg_35\); + + \c$case_alt_69\ <= to_signed(1,2) when \c$case_alt_selection_res_52\ else + \c$case_alt_70\; + + \c$case_alt_selection_res_53\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) <= fm2_15) and (((resize(unsigned(std_logic_vector(\c$app_arg_34\)),5)) >= fm1_15) and \c$app_arg_35\); + + \c$case_alt_70\ <= to_signed(-1,2) when \c$case_alt_selection_res_53\ else + \c$vec_20\(i_3); + + fm1_15 <= result_45.Tup10_sel8_unsigned_8; + + fm2_15 <= result_45.Tup10_sel9_unsigned_9; + + \c$app_arg_35\ <= \c$vec_20\(i_3) = to_signed(0,2); + + tm1_15 <= result_45.Tup10_sel6_unsigned_6; + + tm2_15 <= result_45.Tup10_sel7_unsigned_7; + + mm1_15 <= result_45.Tup10_sel4_unsigned_4; + + mm2_15 <= result_45.Tup10_sel5_unsigned_5; + + ff1_15 <= result_45.Tup10_sel2_unsigned_2; + + ff2_15 <= result_45.Tup10_sel3_unsigned_3; + + tt1_15 <= result_45.Tup10_sel0_unsigned_0; + + tt2_15 <= result_45.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_9 : block + signal vec_index_9 : integer range 0 to 12-1; + begin + vec_index_9 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_19\ <= \c$ds_app_arg_21\(vec_index_9); + end block; + -- index end + + result_44 <= ( Tup2_3_sel0_array_of_signed_2 => \c$app_arg_18\ + , Tup2_3_sel1_boolean => \c$app_arg_19\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_22_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_22\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_22\ <= result_46.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_45 <= result_46.Tup2_0_sel1_Tup10; + + result_46 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_22\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_11.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_11.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_11.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_11.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_11.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_11.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_11.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_11.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_11.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_11.Tup10_sel9_unsigned_9 ) ); + + opcode_11 <= \c$ds_app_arg_22\.Tup3_sel0_unsigned; + + ds4_selection_res_11 <= ((opcode_11 = to_unsigned(0,1)) and (start or start)) or ((opcode_11 = to_unsigned(1,1)) and start); + + ds4_11 <= \c$ds_app_arg_22\.Tup3_sel1_Tup10_0 when ds4_selection_res_11 else + \c$ds_app_arg_22\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_23_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_23\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_23\ <= result_48.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_47 <= result_48.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_54\ <= (to_unsigned(0,5) <= tt2_6) and (to_unsigned(0,5) >= tt1_6); + + \c$case_alt_30\ <= to_signed(1,2) when \c$case_alt_selection_res_54\ else + \c$case_alt_31\; + + \c$case_alt_selection_res_55\ <= (to_unsigned(0,5) <= ff2_6) and (to_unsigned(0,5) >= ff1_6); + + \c$case_alt_31\ <= to_signed(-1,2) when \c$case_alt_selection_res_55\ else + \c$case_alt_32\; + + \c$case_alt_selection_res_56\ <= (to_unsigned(0,5) <= mm2_6) and (to_unsigned(0,5) >= mm1_6); + + \c$case_alt_32\ <= to_signed(0,2) when \c$case_alt_selection_res_56\ else + \c$case_alt_33\; + + \c$case_alt_selection_res_57\ <= (to_unsigned(0,5) <= tm2_6) and ((to_unsigned(0,5) >= tm1_6) and \c$app_arg_20\); + + \c$case_alt_33\ <= to_signed(1,2) when \c$case_alt_selection_res_57\ else + \c$case_alt_34\; + + \c$case_alt_selection_res_58\ <= (to_unsigned(0,5) <= fm2_6) and ((to_unsigned(0,5) >= fm1_6) and \c$app_arg_20\); + + \c$vec_21\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_23\))); + + \c$case_alt_sel_alt_131\ <= (\c$vec_21\(0 to 1-1),\c$vec_21\(1 to \c$vec_21\'high)); + + \c$case_alt_34\ <= to_signed(-1,2) when \c$case_alt_selection_res_58\ else + \c$case_alt_sel_alt_131\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_6 <= result_49.Tup10_sel8_unsigned_8; + + fm2_6 <= result_49.Tup10_sel9_unsigned_9; + + \c$vec_22\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_23\))); + + \c$app_arg_20_28\ <= (\c$vec_22\(0 to 1-1),\c$vec_22\(1 to \c$vec_22\'high)); + + \c$app_arg_20\ <= \c$app_arg_20_28\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_6 <= result_49.Tup10_sel6_unsigned_6; + + tm2_6 <= result_49.Tup10_sel7_unsigned_7; + + mm1_6 <= result_49.Tup10_sel4_unsigned_4; + + mm2_6 <= result_49.Tup10_sel5_unsigned_5; + + ff1_6 <= result_49.Tup10_sel2_unsigned_2; + + ff2_6 <= result_49.Tup10_sel3_unsigned_3; + + tt1_6 <= result_49.Tup10_sel0_unsigned_0; + + tt2_6 <= result_49.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_10 : block + signal vec_index_10 : integer range 0 to 1-1; + begin + vec_index_10 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_21\ <= \c$ds_app_arg_23\(vec_index_10); + end block; + -- index end + + result_48 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_30\) + , Tup2_1_sel1_boolean => \c$app_arg_21\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_24_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_24\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_24\ <= result_50.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_49 <= result_50.Tup2_0_sel1_Tup10; + + result_50 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_24\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_12.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_12.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_12.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_12.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_12.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_12.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_12.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_12.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_12.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_12.Tup10_sel9_unsigned_9 ) ); + + opcode_12 <= \c$ds_app_arg_24\.Tup3_sel0_unsigned; + + ds4_selection_res_12 <= ((opcode_12 = to_unsigned(0,1)) and (result_55 or result_51)) or ((opcode_12 = to_unsigned(1,1)) and result_55); + + ds4_12 <= \c$ds_app_arg_24\.Tup3_sel1_Tup10_0 when ds4_selection_res_12 else + \c$ds_app_arg_24\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_25_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_25\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_25\ <= result_52.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_51 <= result_52.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_59\ <= (to_unsigned(0,5) <= tt2_7) and (to_unsigned(0,5) >= tt1_7); + + \c$case_alt_35\ <= to_signed(1,2) when \c$case_alt_selection_res_59\ else + \c$case_alt_36\; + + \c$case_alt_selection_res_60\ <= (to_unsigned(0,5) <= ff2_7) and (to_unsigned(0,5) >= ff1_7); + + \c$case_alt_36\ <= to_signed(-1,2) when \c$case_alt_selection_res_60\ else + \c$case_alt_37\; + + \c$case_alt_selection_res_61\ <= (to_unsigned(0,5) <= mm2_7) and (to_unsigned(0,5) >= mm1_7); + + \c$case_alt_37\ <= to_signed(0,2) when \c$case_alt_selection_res_61\ else + \c$case_alt_38\; + + \c$case_alt_selection_res_62\ <= (to_unsigned(0,5) <= tm2_7) and ((to_unsigned(0,5) >= tm1_7) and \c$app_arg_22\); + + \c$case_alt_38\ <= to_signed(1,2) when \c$case_alt_selection_res_62\ else + \c$case_alt_39\; + + \c$case_alt_selection_res_63\ <= (to_unsigned(0,5) <= fm2_7) and ((to_unsigned(0,5) >= fm1_7) and \c$app_arg_22\); + + \c$vec_23\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_25\))); + + \c$case_alt_sel_alt_143\ <= (\c$vec_23\(0 to 1-1),\c$vec_23\(1 to \c$vec_23\'high)); + + \c$case_alt_39\ <= to_signed(-1,2) when \c$case_alt_selection_res_63\ else + \c$case_alt_sel_alt_143\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_7 <= result_53.Tup10_sel8_unsigned_8; + + fm2_7 <= result_53.Tup10_sel9_unsigned_9; + + \c$vec_24\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_25\))); + + \c$app_arg_22_31\ <= (\c$vec_24\(0 to 1-1),\c$vec_24\(1 to \c$vec_24\'high)); + + \c$app_arg_22\ <= \c$app_arg_22_31\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_7 <= result_53.Tup10_sel6_unsigned_6; + + tm2_7 <= result_53.Tup10_sel7_unsigned_7; + + mm1_7 <= result_53.Tup10_sel4_unsigned_4; + + mm2_7 <= result_53.Tup10_sel5_unsigned_5; + + ff1_7 <= result_53.Tup10_sel2_unsigned_2; + + ff2_7 <= result_53.Tup10_sel3_unsigned_3; + + tt1_7 <= result_53.Tup10_sel0_unsigned_0; + + tt2_7 <= result_53.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_11 : block + signal vec_index_11 : integer range 0 to 1-1; + begin + vec_index_11 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_23\ <= \c$ds_app_arg_25\(vec_index_11); + end block; + -- index end + + result_52 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_35\) + , Tup2_1_sel1_boolean => \c$app_arg_23\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_26_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_26\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_26\ <= result_54.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_53 <= result_54.Tup2_0_sel1_Tup10; + + result_54 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_26\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_13.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_13.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_13.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_13.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_13.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_13.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_13.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_13.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_13.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_13.Tup10_sel9_unsigned_9 ) ); + + opcode_13 <= \c$ds_app_arg_26\.Tup3_sel0_unsigned; + + ds4_selection_res_13 <= ((opcode_13 = to_unsigned(0,1)) and (dry or dry)) or ((opcode_13 = to_unsigned(1,1)) and dry); + + ds4_13 <= \c$ds_app_arg_26\.Tup3_sel1_Tup10_0 when ds4_selection_res_13 else + \c$ds_app_arg_26\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_27_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_27\ <= Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_27\ <= result_56.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_55 <= result_56.Tup2_1_sel1_boolean; + + \c$case_alt_selection_res_64\ <= (to_unsigned(0,5) <= tt2_8) and (to_unsigned(0,5) >= tt1_8); + + \c$case_alt_40\ <= to_signed(1,2) when \c$case_alt_selection_res_64\ else + \c$case_alt_41\; + + \c$case_alt_selection_res_65\ <= (to_unsigned(0,5) <= ff2_8) and (to_unsigned(0,5) >= ff1_8); + + \c$case_alt_41\ <= to_signed(-1,2) when \c$case_alt_selection_res_65\ else + \c$case_alt_42\; + + \c$case_alt_selection_res_66\ <= (to_unsigned(0,5) <= mm2_8) and (to_unsigned(0,5) >= mm1_8); + + \c$case_alt_42\ <= to_signed(0,2) when \c$case_alt_selection_res_66\ else + \c$case_alt_43\; + + \c$case_alt_selection_res_67\ <= (to_unsigned(0,5) <= tm2_8) and ((to_unsigned(0,5) >= tm1_8) and \c$app_arg_24\); + + \c$case_alt_43\ <= to_signed(1,2) when \c$case_alt_selection_res_67\ else + \c$case_alt_44\; + + \c$case_alt_selection_res_68\ <= (to_unsigned(0,5) <= fm2_8) and ((to_unsigned(0,5) >= fm1_8) and \c$app_arg_24\); + + \c$vec_25\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_27\))); + + \c$case_alt_sel_alt_155\ <= (\c$vec_25\(0 to 1-1),\c$vec_25\(1 to \c$vec_25\'high)); + + \c$case_alt_44\ <= to_signed(-1,2) when \c$case_alt_selection_res_68\ else + \c$case_alt_sel_alt_155\.Tup2_5_sel0_array_of_signed_2_0(0); + + fm1_8 <= result_57.Tup10_sel8_unsigned_8; + + fm2_8 <= result_57.Tup10_sel9_unsigned_9; + + \c$vec_26\ <= (Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(Prop_combined_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop_combined_topEntity_types.array_of_signed_2'(\c$ds_app_arg_27\))); + + \c$app_arg_24_34\ <= (\c$vec_26\(0 to 1-1),\c$vec_26\(1 to \c$vec_26\'high)); + + \c$app_arg_24\ <= \c$app_arg_24_34\.Tup2_5_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_8 <= result_57.Tup10_sel6_unsigned_6; + + tm2_8 <= result_57.Tup10_sel7_unsigned_7; + + mm1_8 <= result_57.Tup10_sel4_unsigned_4; + + mm2_8 <= result_57.Tup10_sel5_unsigned_5; + + ff1_8 <= result_57.Tup10_sel2_unsigned_2; + + ff2_8 <= result_57.Tup10_sel3_unsigned_3; + + tt1_8 <= result_57.Tup10_sel0_unsigned_0; + + tt2_8 <= result_57.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_12 : block + signal vec_index_12 : integer range 0 to 1-1; + begin + vec_index_12 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_25\ <= \c$ds_app_arg_27\(vec_index_12); + end block; + -- index end + + result_56 <= ( Tup2_1_sel0_array_of_signed_2 => Prop_combined_topEntity_types.array_of_signed_2'(0 => \c$case_alt_40\) + , Tup2_1_sel1_boolean => \c$app_arg_25\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_28_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_28\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_28\ <= result_58.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_57 <= result_58.Tup2_0_sel1_Tup10; + + result_58 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_28\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_14.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_14.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_14.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_14.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_14.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_14.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_14.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_14.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_14.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_14.Tup10_sel9_unsigned_9 ) ); + + opcode_14 <= \c$ds_app_arg_28\.Tup3_sel0_unsigned; + + ds4_selection_res_14 <= ((opcode_14 = to_unsigned(0,1)) and (drain or drain)) or ((opcode_14 = to_unsigned(1,1)) and drain); + + ds4_14 <= \c$ds_app_arg_28\.Tup3_sel1_Tup10_0 when ds4_selection_res_14 else + \c$ds_app_arg_28\.Tup3_sel2_Tup10_1; + + ccase_alt_0 <= ccase_alt.Tup5_sel0_boolean_0; + + ccase_alt_1 <= ccase_alt.Tup5_sel1_boolean_1; + + ccase_alt_2 <= ccase_alt.Tup5_sel2_boolean_2; + + ccase_alt_3 <= ccase_alt.Tup5_sel3_boolean_3; + + ccase_alt_4 <= ccase_alt.Tup5_sel4_boolean_4; + + +end; + diff --git a/tests/washing_machine/properties/prop1.hs b/tests/washing_machine/properties/prop1.hs new file mode 100644 index 0000000..9298ce8 --- /dev/null +++ b/tests/washing_machine/properties/prop1.hs @@ -0,0 +1,36 @@ +module Prop1 where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +queue_mealy1 inp = mealy queue (0:>Nil) inp +queue_mealy2 inp = mealy queue (0:>Nil) inp +queue_mealy3 inp = mealy queue (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp + +prop1 (inp1,inp2) = queue_mealy1 (processingElement_mealy_or (bundle ( queue_mealy2 (processingElement_mealy_not (bundle (inp1,inp1))), +queue_mealy3 (processingElement_mealy_not (bundle (inp2,inp2))) ) ) ) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool), Signal System (Bool)) + -> Signal System ( Bool) +topEntity = exposeClockResetEnable prop1 + +testBench :: Signal System Bool +testBench = done + where + testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False]) + testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False]) + expectOutput = outputVerifier' clk rst $(listToVecTH [False ::Bool, False, True , True, False, True, True, False, True, True, False, False, False, False, True]) + done = expectOutput (topEntity clk rst en (testInput1, testInput2)) + en = enableGen + clk = tbSystemClockGen (not <$> done) + rst = systemResetGen diff --git a/tests/washing_machine/properties/prop2.hs b/tests/washing_machine/properties/prop2.hs new file mode 100644 index 0000000..821d289 --- /dev/null +++ b/tests/washing_machine/properties/prop2.hs @@ -0,0 +1,37 @@ +module Prop2 where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +queue_mealy4 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy5 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy6 inp = mealy queue (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp + +processingElement_mealy_box inp = mealy processingElement (1,(31,31,31,31,0,0,11,11,31,31),(31,31,7,11,0,0,31,31,31,31)) inp + +prop2 (inp1,inp2) = queue_mealy6 (processingElement_mealy_or (bundle (queue_mealy5 (processingElement_mealy_not (bundle (inp1,inp1)) ) , queue_mealy4 (processingElement_mealy_box (bundle (inp2,inp2) ) ) ))) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool), Signal System (Bool)) + -> Signal System ( Bool) +topEntity = exposeClockResetEnable prop2 + +testBench :: Signal System Bool +testBench = done + where + testInput1 = stimuliGenerator clk rst $(listToVecTH [True::Bool , False, False, False, False, False, False, False, False, False, False, False, False, False, False, False]) + testInput2 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False, True, True, True, True, True, True, True,False, False, False]) + expectOutput = outputVerifier' clk rst $(listToVecTH [False ::Bool,False, False, False, False, False, False, False, False, False, False, False, False, False, True , True, True, True , True, True, True, True, True, True, True , True, True, True,True]) + done = expectOutput (topEntity clk rst en (testInput1, testInput2)) + en = enableGen + clk = tbSystemClockGen (not <$> done) + rst = systemResetGen diff --git a/tests/washing_machine/properties/prop3.hs b/tests/washing_machine/properties/prop3.hs new file mode 100644 index 0000000..33325aa --- /dev/null +++ b/tests/washing_machine/properties/prop3.hs @@ -0,0 +1,38 @@ +module Prop3 where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +queue_mealy7 inp = mealy queue (0:>Nil) inp +queue_mealy8 inp = mealy queue (0:>Nil) inp +queue_mealy9 inp = mealy queue (0:>Nil) inp +queue_mealy10 inp = mealy queue (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp + +processingElement_mealy_next inp = mealy processingElement (1,(1,1,31,31,0,0,31,31,31,31),(31,31,1,1,0,0,31,31,31,31)) inp + +prop3 (inp1,inp2) = queue_mealy10 (processingElement_mealy_or (bundle (queue_mealy9 (processingElement_mealy_not (bundle (inp1,inp1)) ) , queue_mealy8 (processingElement_mealy_next (bundle (queue_mealy7 (processingElement_mealy_or (bundle (inp1, inp2) ) ), queue_mealy7 (processingElement_mealy_or (bundle (inp1, inp2) ) ) ) ) )))) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool), Signal System (Bool)) + -> Signal System ( Bool) +topEntity = exposeClockResetEnable prop3 + +testBench :: Signal System Bool +testBench = done + where + testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, False, False, False, False, False, False, False, False, False, False, False]) + testInput2 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False, True, True, True, True, True, True, True,False, False, False]) + expectOutput = outputVerifier' clk rst $(listToVecTH [False::Bool , False, True, True, False, True, True, True, True, True, True, True, True , True, True, True,True]) + done = expectOutput (topEntity clk rst en (testInput1, testInput2)) + en = enableGen + clk = tbSystemClockGen (not <$> done) + rst = systemResetGen diff --git a/tests/washing_machine/properties/prop4.hs b/tests/washing_machine/properties/prop4.hs new file mode 100644 index 0000000..ef77b5e --- /dev/null +++ b/tests/washing_machine/properties/prop4.hs @@ -0,0 +1,37 @@ +module Prop4 where +import Clash.Explicit.Testbench +import Clash.Prelude +import ProcessingElement(processingElement) +import Queue(queue,queuetest) +import Queue30(queue30,queuetest30) + +queue_mealy11 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy12 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>Nil) inp +queue_mealy13 inp = mealy queue (0:>Nil) inp + +processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp + +processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp + +processingElement_mealy_diamond inp = mealy processingElement (1,(4,6,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,6,6)) inp + +prop4 (inp1,inp2) = queue_mealy13 (processingElement_mealy_or (bundle (queue_mealy11 (processingElement_mealy_not (bundle (inp1,inp1)) ), queue_mealy12 (processingElement_mealy_diamond (bundle (inp2,inp2)) ) )) ) + +topEntity + :: Clock System + -> Reset System + -> Enable System + -> (Signal System (Bool), Signal System (Bool)) + -> Signal System ( Bool) +topEntity = exposeClockResetEnable prop4 + +testBench :: Signal System Bool +testBench = done + where + testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, True, False, False, False, False, False, False, False, False, False, False, False, False]) + testInput2 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False, True, True, True, True, True, True, True,False, False, False]) + expectOutput = outputVerifier' clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False,False, True, True, True, True, True, True, True,False, False, False]) + done = expectOutput (topEntity clk rst en (testInput1, testInput2)) + en = enableGen + clk = tbSystemClockGen (not <$> done) + rst = systemResetGen diff --git a/tests/washing_machine/properties/props.txt b/tests/washing_machine/properties/props.txt new file mode 100644 index 0000000..95739a8 --- /dev/null +++ b/tests/washing_machine/properties/props.txt @@ -0,0 +1,6 @@ +---------------------------------------------WASHING_MACHINE---------------------------------------------- +(1) !(drain ^ dry) ---> satisfied by prog1_3 +(2) START -> box [7,11] wash ---> satisfied by prog1, sometimes by prog3 +(3) fill -> O (fill v soak ) ---> satisfied by prog1_3 +(4) start -> Dia [4,6] soak ---> satisfied by prog1_3f +(5) start U [0,19] dry ---> should be satisfied only by prog3 \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/Prop1_testBench_types.vhdl b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/Prop1_testBench_types.vhdl new file mode 100644 index 0000000..9a83b1d --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/Prop1_testBench_types.vhdl @@ -0,0 +1,213 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop1_testBench_types is + + + subtype rst_System is std_logic; + type array_of_boolean is array (integer range <>) of boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + subtype index_13 is unsigned(3 downto 0); + subtype index_29 is unsigned(4 downto 0); + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + subtype index_15 is unsigned(3 downto 0); + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_1_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (value : array_of_boolean) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_boolean; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; +end; + +package body Prop1_testBench_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (value : array_of_boolean) return std_logic_vector is + alias ivalue : array_of_boolean(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 1); + begin + for i in ivalue'range loop + result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_boolean is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_boolean(0 to slv'length / 1 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 1 to (i+1) * 1 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2_0) & toSLV(p.Tup2_1_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/clash-manifest.json new file mode 100644 index 0000000..5aa7670 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/clash-manifest.json @@ -0,0 +1,63 @@ +{ + "components": [ + "testBench" + ], + "flags": [ + 20, + 20 + ], + "hash": "d15a15fa2c6dfabe3fd99e0e7002213667bdda40175e353c8fa219a97eac7948", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "Prop1_testBench_types.vhdl", + "sha256": "094e73067af55e92ae5cb0b42abe0d522bc49d7e17eb56493139553781f7b381" + }, + { + "name": "testBench.vhdl", + "sha256": "2e12df463ffa39c26c3b96ba46ef354c6338baaee2c9b9fb231cb62f5408cb7c" + }, + { + "name": "testBench_slv2string_FD7FE0FDE5409B5E.vhdl", + "sha256": "76ad6e6a41f26803fce0edeea54f88c878437b1a39bfb81fff18923737be7966" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "testBench" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench.vhdl b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench.vhdl new file mode 100644 index 0000000..bbfeef2 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench.vhdl @@ -0,0 +1,859 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop1_testBench_types.all; +use testBench_slv2string_FD7FE0FDE5409B5E.all; + +entity testBench is + port(result : out boolean); +end; + +architecture structural of testBench is + signal \c$ds_app_arg\ : Prop1_testBench_types.index_13; + signal \c$ds_app_arg_0\ : boolean; + signal s : Prop1_testBench_types.index_13 := to_unsigned(0,4); + -- prop1.hs:34:5-7 + signal \Prop1.testBench_clk\ : Prop1_testBench_types.clk_System; + signal z : Prop1_testBench_types.index_29; + signal result_1 : Prop1_testBench_types.index_15; + signal \c$ds_app_arg_1\ : boolean; + signal \c$result_rec\ : boolean; + signal s_0 : Prop1_testBench_types.index_15 := to_unsigned(0,4); + signal f2 : boolean; + signal \f'\ : boolean := false; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg_2\ : Prop1_testBench_types.array_of_signed_2(0 to 0) := Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_2 : boolean; + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_3 : Prop1_testBench_types.Tup2; + -- prop1.hs:12:1-124 + signal \c$ds_app_arg_3\ : Prop1_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_4 : Prop1_testBench_types.Tup10; + signal result_5 : Prop1_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop1_testBench_types.Tup10; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg_4\ : Prop1_testBench_types.array_of_signed_2(0 to 0) := Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_6 : boolean; + signal \c$case_alt_4\ : signed(1 downto 0); + signal \c$case_alt_5\ : signed(1 downto 0); + signal \c$case_alt_6\ : signed(1 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_0 : unsigned(4 downto 0); + signal \c$app_arg_1\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_0 : unsigned(4 downto 0); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_7 : Prop1_testBench_types.Tup2; + -- prop1.hs:14:1-125 + signal \c$ds_app_arg_5\ : Prop1_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_8 : Prop1_testBench_types.Tup10; + signal result_9 : Prop1_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop1_testBench_types.Tup10; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg_6\ : Prop1_testBench_types.array_of_signed_2(0 to 0) := Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_10 : boolean; + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_3\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_11 : Prop1_testBench_types.Tup2; + -- prop1.hs:14:1-125 + signal \c$ds_app_arg_7\ : Prop1_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_12 : Prop1_testBench_types.Tup10; + signal result_13 : Prop1_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop1_testBench_types.Tup10; + signal \c$ds_app_arg_8\ : Prop1_testBench_types.index_13; + signal \c$ds_app_arg_9\ : boolean; + signal s_1 : Prop1_testBench_types.index_13 := to_unsigned(0,4); + -- prop1.hs:27:1-9 + signal \c$Prop1.testBench_app_arg\ : Prop1_testBench_types.rst_System; + signal \c$ds_app_arg_selection_res\ : boolean; + signal \c$vec\ : Prop1_testBench_types.array_of_boolean(0 to 12); + signal result_selection_res : boolean; + signal \c$vec_0\ : Prop1_testBench_types.array_of_boolean(0 to 14); + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec_1\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop1_testBench_types.Tup2_1; + signal \c$vec_2\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop1_testBench_types.Tup2_1; + signal ds4_selection_res : boolean; + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + signal \c$vec_3\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_21\ : Prop1_testBench_types.Tup2_1; + signal \c$vec_4\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_1_2\ : Prop1_testBench_types.Tup2_1; + signal ds4_selection_res_0 : boolean; + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + signal \c$vec_5\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_33\ : Prop1_testBench_types.Tup2_1; + signal \c$vec_6\ : Prop1_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_3_5\ : Prop1_testBench_types.Tup2_1; + signal ds4_selection_res_1 : boolean; + signal \c$ds_app_arg_selection_res_0\ : boolean; + signal \c$vec_7\ : Prop1_testBench_types.array_of_boolean(0 to 12); + +begin + \c$ds_app_arg_selection_res\ <= s < to_unsigned(12,4); + + \c$ds_app_arg\ <= s + to_unsigned(1,4) when \c$ds_app_arg_selection_res\ else + s; + + \c$vec\ <= Prop1_testBench_types.array_of_boolean'( false + , false + , true + , false + , false + , true + , false + , false + , true + , true + , true + , true + , false ); + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 13-1; + begin + vec_index <= to_integer((signed(std_logic_vector(resize(s,64))))) + -- pragma translate_off + mod 13 + -- pragma translate_on + ; + \c$ds_app_arg_0\ <= \c$vec\(vec_index); + end block; + -- index end + + -- register begin + s_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + s <= to_unsigned(0,4); + elsif rising_edge(\Prop1.testBench_clk\) then + s <= \c$ds_app_arg\; + end if; + end process; + -- register end + + -- tbClockGen begin + -- pragma translate_off + clkGen : process is + constant half_periodH : time := 10000000 fs / 2; + constant half_periodL : time := 10000000 fs - half_periodH; + begin + \Prop1.testBench_clk\ <= '0'; + wait for 10000 ps; + while (not \c$result_rec\) loop + \Prop1.testBench_clk\ <= not \Prop1.testBench_clk\; + wait for half_periodH; + \Prop1.testBench_clk\ <= not \Prop1.testBench_clk\; + wait for half_periodL; + end loop; + wait; + end process; + -- pragma translate_on + -- tbClockGen end + + z <= resize(s_0,5) + resize(to_unsigned(1,4),5); + + result_selection_res <= z > to_unsigned(14,5); + + result_1 <= to_unsigned(14,4) when result_selection_res else + resize(z,4); + + \c$vec_0\ <= Prop1_testBench_types.array_of_boolean'( false + , false + , true + , true + , false + , true + , true + , false + , true + , true + , false + , false + , false + , false + , true ); + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 15-1; + begin + vec_index_0 <= to_integer((signed(std_logic_vector(resize(s_0,64))))) + -- pragma translate_off + mod 15 + -- pragma translate_on + ; + \c$ds_app_arg_1\ <= \c$vec_0\(vec_index_0); + end block; + -- index end + + \c$result_rec\ <= \f'\ when \f'\ else + f2; + + -- register begin + s_0_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + s_0 <= to_unsigned(0,4); + elsif rising_edge(\Prop1.testBench_clk\) then + s_0 <= result_1; + end if; + end process; + -- register end + + -- assert begin + r_assert : block + -- pragma translate_off + signal actual : boolean; + signal expected : boolean; + -- pragma translate_on + begin + -- pragma translate_off + actual <= result_2; + expected <= \c$ds_app_arg_1\; + process(\Prop1.testBench_clk\) is + begin + if (rising_edge(\Prop1.testBench_clk\)) then + assert (toSLV(actual) = toSLV(expected)) report (("outputVerifier") & ", expected: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(expected)) & ", actual: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(actual))) severity error; + end if; + end process; + -- pragma translate_on + f2 <= \f'\; + end block; + -- assert end + + -- register begin + f_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \f'\ <= false; + elsif rising_edge(\Prop1.testBench_clk\) then + \f'\ <= (s_0 = to_unsigned(14,4)); + end if; + end process; + -- register end + + -- register begin + cds_app_arg_2_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_2\ <= Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_2\ <= result_3.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec_1\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1 <= result_4.Tup10_sel8_unsigned_8; + + fm2 <= result_4.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$app_arg_7\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_4.Tup10_sel6_unsigned_6; + + tm2 <= result_4.Tup10_sel7_unsigned_7; + + mm1 <= result_4.Tup10_sel4_unsigned_4; + + mm2 <= result_4.Tup10_sel5_unsigned_5; + + ff1 <= result_4.Tup10_sel2_unsigned_2; + + ff2 <= result_4.Tup10_sel3_unsigned_3; + + tt1 <= result_4.Tup10_sel0_unsigned_0; + + tt2 <= result_4.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg_2\(vec_index_1); + end block; + -- index end + + result_3 <= ( Tup2_sel0_array_of_signed_2 => Prop1_testBench_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_3_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_3\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_3\ <= result_5.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_0_sel1_Tup10; + + result_5 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_3\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_3\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_10 or result_6)) or ((opcode = to_unsigned(1,1)) and result_10); + + ds4 <= \c$ds_app_arg_3\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_3\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_4_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_4\ <= Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_4\ <= result_7.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_sel1_boolean; + + \c$case_alt_selection_res_4\ <= (to_unsigned(0,5) <= tt2_0) and (to_unsigned(0,5) >= tt1_0); + + \c$case_alt_4\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_5\; + + \c$case_alt_selection_res_5\ <= (to_unsigned(0,5) <= ff2_0) and (to_unsigned(0,5) >= ff1_0); + + \c$case_alt_5\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_6\; + + \c$case_alt_selection_res_6\ <= (to_unsigned(0,5) <= mm2_0) and (to_unsigned(0,5) >= mm1_0); + + \c$case_alt_6\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_7\; + + \c$case_alt_selection_res_7\ <= (to_unsigned(0,5) <= tm2_0) and ((to_unsigned(0,5) >= tm1_0) and \c$app_arg_1\); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_8\ <= (to_unsigned(0,5) <= fm2_0) and ((to_unsigned(0,5) >= fm1_0) and \c$app_arg_1\); + + \c$vec_3\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$case_alt_sel_alt_21\ <= (\c$vec_3\(0 to 1-1),\c$vec_3\(1 to \c$vec_3\'high)); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$case_alt_sel_alt_21\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1_0 <= result_8.Tup10_sel8_unsigned_8; + + fm2_0 <= result_8.Tup10_sel9_unsigned_9; + + \c$vec_4\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$app_arg_1_2\ <= (\c$vec_4\(0 to 1-1),\c$vec_4\(1 to \c$vec_4\'high)); + + \c$app_arg_1\ <= \c$app_arg_1_2\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_0 <= result_8.Tup10_sel6_unsigned_6; + + tm2_0 <= result_8.Tup10_sel7_unsigned_7; + + mm1_0 <= result_8.Tup10_sel4_unsigned_4; + + mm2_0 <= result_8.Tup10_sel5_unsigned_5; + + ff1_0 <= result_8.Tup10_sel2_unsigned_2; + + ff2_0 <= result_8.Tup10_sel3_unsigned_3; + + tt1_0 <= result_8.Tup10_sel0_unsigned_0; + + tt2_0 <= result_8.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 1-1; + begin + vec_index_2 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_4\(vec_index_2); + end block; + -- index end + + result_7 <= ( Tup2_sel0_array_of_signed_2 => Prop1_testBench_types.array_of_signed_2'(0 => \c$case_alt_4\) + , Tup2_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_5_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_5\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_5\ <= result_9.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_0_sel1_Tup10; + + result_9 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_5\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_5\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (\c$ds_app_arg_9\ or \c$ds_app_arg_9\)) or ((opcode_0 = to_unsigned(1,1)) and \c$ds_app_arg_9\); + + ds4_0 <= \c$ds_app_arg_5\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_5\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_6_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_6\ <= Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_6\ <= result_11.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_sel1_boolean; + + \c$case_alt_selection_res_9\ <= (to_unsigned(0,5) <= tt2_1) and (to_unsigned(0,5) >= tt1_1); + + \c$case_alt_9\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_10\ <= (to_unsigned(0,5) <= ff2_1) and (to_unsigned(0,5) >= ff1_1); + + \c$case_alt_10\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_11\ <= (to_unsigned(0,5) <= mm2_1) and (to_unsigned(0,5) >= mm1_1); + + \c$case_alt_11\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_12\; + + \c$case_alt_selection_res_12\ <= (to_unsigned(0,5) <= tm2_1) and ((to_unsigned(0,5) >= tm1_1) and \c$app_arg_3\); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_13\ <= (to_unsigned(0,5) <= fm2_1) and ((to_unsigned(0,5) >= fm1_1) and \c$app_arg_3\); + + \c$vec_5\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$case_alt_sel_alt_33\ <= (\c$vec_5\(0 to 1-1),\c$vec_5\(1 to \c$vec_5\'high)); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$case_alt_sel_alt_33\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1_1 <= result_12.Tup10_sel8_unsigned_8; + + fm2_1 <= result_12.Tup10_sel9_unsigned_9; + + \c$vec_6\ <= (Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(Prop1_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$app_arg_3_5\ <= (\c$vec_6\(0 to 1-1),\c$vec_6\(1 to \c$vec_6\'high)); + + \c$app_arg_3\ <= \c$app_arg_3_5\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_1 <= result_12.Tup10_sel6_unsigned_6; + + tm2_1 <= result_12.Tup10_sel7_unsigned_7; + + mm1_1 <= result_12.Tup10_sel4_unsigned_4; + + mm2_1 <= result_12.Tup10_sel5_unsigned_5; + + ff1_1 <= result_12.Tup10_sel2_unsigned_2; + + ff2_1 <= result_12.Tup10_sel3_unsigned_3; + + tt1_1 <= result_12.Tup10_sel0_unsigned_0; + + tt2_1 <= result_12.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_3 : block + signal vec_index_3 : integer range 0 to 1-1; + begin + vec_index_3 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_6\(vec_index_3); + end block; + -- index end + + result_11 <= ( Tup2_sel0_array_of_signed_2 => Prop1_testBench_types.array_of_signed_2'(0 => \c$case_alt_9\) + , Tup2_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_7_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + \c$ds_app_arg_7\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop1.testBench_clk\) then + \c$ds_app_arg_7\ <= result_13.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_12 <= result_13.Tup2_0_sel1_Tup10; + + result_13 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_7\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_7\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_0\)) or ((opcode_1 = to_unsigned(1,1)) and \c$ds_app_arg_0\); + + ds4_1 <= \c$ds_app_arg_7\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_7\.Tup3_sel2_Tup10_1; + + \c$ds_app_arg_selection_res_0\ <= s_1 < to_unsigned(12,4); + + \c$ds_app_arg_8\ <= s_1 + to_unsigned(1,4) when \c$ds_app_arg_selection_res_0\ else + s_1; + + \c$vec_7\ <= Prop1_testBench_types.array_of_boolean'( true + , true + , true + , true + , true + , true + , false + , false + , true + , true + , true + , true + , false ); + + -- index begin + indexVec_4 : block + signal vec_index_4 : integer range 0 to 13-1; + begin + vec_index_4 <= to_integer((signed(std_logic_vector(resize(s_1,64))))) + -- pragma translate_off + mod 13 + -- pragma translate_on + ; + \c$ds_app_arg_9\ <= \c$vec_7\(vec_index_4); + end block; + -- index end + + -- register begin + s_1_register : process(\Prop1.testBench_clk\,\c$Prop1.testBench_app_arg\) + begin + if \c$Prop1.testBench_app_arg\ = '1' then + s_1 <= to_unsigned(0,4); + elsif rising_edge(\Prop1.testBench_clk\) then + s_1 <= \c$ds_app_arg_8\; + end if; + end process; + -- register end + + -- resetGen begin + resetGen : block + constant reset_delay : time := 10000 ps - 1 ps + (integer'(1) * 10000 ps); + begin + -- pragma translate_off + \c$Prop1.testBench_app_arg\ + <= '1', + '0' after reset_delay; + -- pragma translate_on + end block; + -- resetGen end + + result <= \c$result_rec\; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl new file mode 100644 index 0000000..dcabb4a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl @@ -0,0 +1,24 @@ +-- helper function of Clash.Explicit.Testbench.assert +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING; +end; + +package body testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING is + variable result : string (1 to slv'length); + variable res_l : string (1 to 3); + variable r : integer; + begin + r := 1; + for i in slv'range loop + res_l := std_logic'image(slv(i)); + result(r) := res_l(2); + r := r + 1; + end loop; + return result; + end slv2string; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/Prop1_topEntity_types.vhdl b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/Prop1_topEntity_types.vhdl new file mode 100644 index 0000000..aecced4 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/Prop1_topEntity_types.vhdl @@ -0,0 +1,205 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop1_topEntity_types is + + + type Tup2_1 is record + Tup2_1_sel0_boolean_0 : boolean; + Tup2_1_sel1_boolean_1 : boolean; + end record; + subtype rst_System is std_logic; + subtype en_System is boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_2 is record + Tup2_2_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_2_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; +end; + +package body Prop1_topEntity_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_boolean_0) & toSLV(p.Tup2_1_sel1_boolean_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1))); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_array_of_signed_2_0) & toSLV(p.Tup2_2_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/clash-manifest.json new file mode 100644 index 0000000..63ad0bd --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/clash-manifest.json @@ -0,0 +1,101 @@ +{ + "components": [ + "topEntity" + ], + "flags": [ + 20, + 20 + ], + "hash": "f38527c09127dc8c3b603c11c5dec571eadb251542af9bd85e0b6667053c0dfb", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "topEntity.sdc", + "sha256": "13d4c1aafcc09a84d81d3b60d513cb901384a10e27e5a5a16572a600f15895f3" + }, + { + "name": "Prop1_topEntity_types.vhdl", + "sha256": "3460416a2efc22b3b4f76a73a562f0507ff60e1ab50ba9ed72a51d65490d7d06" + }, + { + "name": "topEntity.vhdl", + "sha256": "0a52db2b8c464b6c5dec1c3c9c5e2ceb8b0b67445e6d3693b3bb37701ca88677" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "clk", + "is_clock": true, + "type_name": "clk.Prop1_topEntity_types.clk_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "rst", + "is_clock": false, + "type_name": "rst.Prop1_topEntity_types.rst_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "en", + "is_clock": false, + "type_name": "en.Prop1_topEntity_types.en_System" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_0", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_1", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "topEntity" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.sdc b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.sdc new file mode 100644 index 0000000..885f86a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.sdc @@ -0,0 +1,2 @@ +create_clock -name {clk} -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] + diff --git a/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.vhdl b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.vhdl new file mode 100644 index 0000000..2bff517 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop1/Prop1.topEntity/topEntity.vhdl @@ -0,0 +1,665 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop1_topEntity_types.all; + +entity topEntity is + port(-- clock + clk : in Prop1_topEntity_types.clk_System; + -- reset + rst : in Prop1_topEntity_types.rst_System; + -- enable + en : in Prop1_topEntity_types.en_System; + eta1_0 : in boolean; + eta1_1 : in boolean; + result : out boolean); +end; + +architecture structural of topEntity is + -- prop1.hs:16:1-206 + signal inp1 : boolean; + -- prop1.hs:16:1-206 + signal inp2 : boolean; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg\ : Prop1_topEntity_types.array_of_signed_2(0 to 0) := Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_1 : Prop1_topEntity_types.Tup2; + -- prop1.hs:12:1-124 + signal \c$ds_app_arg_0\ : Prop1_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_2 : Prop1_topEntity_types.Tup10; + signal result_3 : Prop1_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop1_topEntity_types.Tup10; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg_1\ : Prop1_topEntity_types.array_of_signed_2(0 to 0) := Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_4 : boolean; + signal \c$case_alt_4\ : signed(1 downto 0); + signal \c$case_alt_5\ : signed(1 downto 0); + signal \c$case_alt_6\ : signed(1 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_0 : unsigned(4 downto 0); + signal \c$app_arg_1\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_0 : unsigned(4 downto 0); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_5 : Prop1_topEntity_types.Tup2; + -- prop1.hs:14:1-125 + signal \c$ds_app_arg_2\ : Prop1_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_6 : Prop1_topEntity_types.Tup10; + signal result_7 : Prop1_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop1_topEntity_types.Tup10; + -- prop1.hs:8:1-43 + signal \c$ds_app_arg_3\ : Prop1_topEntity_types.array_of_signed_2(0 to 0) := Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_8 : boolean; + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_3\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_9 : Prop1_topEntity_types.Tup2; + -- prop1.hs:14:1-125 + signal \c$ds_app_arg_4\ : Prop1_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_10 : Prop1_topEntity_types.Tup10; + signal result_11 : Prop1_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop1_topEntity_types.Tup10; + signal eta1 : Prop1_topEntity_types.Tup2_1; + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop1_topEntity_types.Tup2_2; + signal \c$vec_0\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop1_topEntity_types.Tup2_2; + signal ds4_selection_res : boolean; + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + signal \c$vec_1\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_21\ : Prop1_topEntity_types.Tup2_2; + signal \c$vec_2\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_1_2\ : Prop1_topEntity_types.Tup2_2; + signal ds4_selection_res_0 : boolean; + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + signal \c$vec_3\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_33\ : Prop1_topEntity_types.Tup2_2; + signal \c$vec_4\ : Prop1_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_3_5\ : Prop1_topEntity_types.Tup2_2; + signal ds4_selection_res_1 : boolean; + +begin + eta1 <= ( Tup2_1_sel0_boolean_0 => eta1_0 + , Tup2_1_sel1_boolean_1 => eta1_1 ); + + inp1 <= eta1.Tup2_1_sel0_boolean_0; + + inp2 <= eta1.Tup2_1_sel1_boolean_1; + + -- register begin + cds_app_arg_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg\ <= Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg\ <= result_1.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result <= result_1.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec\(0 to 1-1),\c$vec\(1 to \c$vec\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1 <= result_2.Tup10_sel8_unsigned_8; + + fm2 <= result_2.Tup10_sel9_unsigned_9; + + \c$vec_0\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$app_arg_7\ <= (\c$vec_0\(0 to 1-1),\c$vec_0\(1 to \c$vec_0\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_2.Tup10_sel6_unsigned_6; + + tm2 <= result_2.Tup10_sel7_unsigned_7; + + mm1 <= result_2.Tup10_sel4_unsigned_4; + + mm2 <= result_2.Tup10_sel5_unsigned_5; + + ff1 <= result_2.Tup10_sel2_unsigned_2; + + ff2 <= result_2.Tup10_sel3_unsigned_3; + + tt1 <= result_2.Tup10_sel0_unsigned_0; + + tt2 <= result_2.Tup10_sel1_unsigned_1; + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 1-1; + begin + vec_index <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg\(vec_index); + end block; + -- index end + + result_1 <= ( Tup2_sel0_array_of_signed_2 => Prop1_topEntity_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_0_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_0\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_0\ <= result_3.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_0_sel1_Tup10; + + result_3 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_0\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_0\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_8 or result_4)) or ((opcode = to_unsigned(1,1)) and result_8); + + ds4 <= \c$ds_app_arg_0\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_0\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_1_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_1\ <= Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_1\ <= result_5.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_sel1_boolean; + + \c$case_alt_selection_res_4\ <= (to_unsigned(0,5) <= tt2_0) and (to_unsigned(0,5) >= tt1_0); + + \c$case_alt_4\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_5\; + + \c$case_alt_selection_res_5\ <= (to_unsigned(0,5) <= ff2_0) and (to_unsigned(0,5) >= ff1_0); + + \c$case_alt_5\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_6\; + + \c$case_alt_selection_res_6\ <= (to_unsigned(0,5) <= mm2_0) and (to_unsigned(0,5) >= mm1_0); + + \c$case_alt_6\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_7\; + + \c$case_alt_selection_res_7\ <= (to_unsigned(0,5) <= tm2_0) and ((to_unsigned(0,5) >= tm1_0) and \c$app_arg_1\); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_8\ <= (to_unsigned(0,5) <= fm2_0) and ((to_unsigned(0,5) >= fm1_0) and \c$app_arg_1\); + + \c$vec_1\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$case_alt_sel_alt_21\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$case_alt_sel_alt_21\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1_0 <= result_6.Tup10_sel8_unsigned_8; + + fm2_0 <= result_6.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$app_arg_1_2\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg_1\ <= \c$app_arg_1_2\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_0 <= result_6.Tup10_sel6_unsigned_6; + + tm2_0 <= result_6.Tup10_sel7_unsigned_7; + + mm1_0 <= result_6.Tup10_sel4_unsigned_4; + + mm2_0 <= result_6.Tup10_sel5_unsigned_5; + + ff1_0 <= result_6.Tup10_sel2_unsigned_2; + + ff2_0 <= result_6.Tup10_sel3_unsigned_3; + + tt1_0 <= result_6.Tup10_sel0_unsigned_0; + + tt2_0 <= result_6.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 1-1; + begin + vec_index_0 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_1\(vec_index_0); + end block; + -- index end + + result_5 <= ( Tup2_sel0_array_of_signed_2 => Prop1_topEntity_types.array_of_signed_2'(0 => \c$case_alt_4\) + , Tup2_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_2_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_2\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_2\ <= result_7.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_0_sel1_Tup10; + + result_7 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_2\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_2\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (inp2 or inp2)) or ((opcode_0 = to_unsigned(1,1)) and inp2); + + ds4_0 <= \c$ds_app_arg_2\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_2\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_3_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_3\ <= Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_3\ <= result_9.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_sel1_boolean; + + \c$case_alt_selection_res_9\ <= (to_unsigned(0,5) <= tt2_1) and (to_unsigned(0,5) >= tt1_1); + + \c$case_alt_9\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_10\ <= (to_unsigned(0,5) <= ff2_1) and (to_unsigned(0,5) >= ff1_1); + + \c$case_alt_10\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_11\ <= (to_unsigned(0,5) <= mm2_1) and (to_unsigned(0,5) >= mm1_1); + + \c$case_alt_11\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_12\; + + \c$case_alt_selection_res_12\ <= (to_unsigned(0,5) <= tm2_1) and ((to_unsigned(0,5) >= tm1_1) and \c$app_arg_3\); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_13\ <= (to_unsigned(0,5) <= fm2_1) and ((to_unsigned(0,5) >= fm1_1) and \c$app_arg_3\); + + \c$vec_3\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$case_alt_sel_alt_33\ <= (\c$vec_3\(0 to 1-1),\c$vec_3\(1 to \c$vec_3\'high)); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$case_alt_sel_alt_33\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1_1 <= result_10.Tup10_sel8_unsigned_8; + + fm2_1 <= result_10.Tup10_sel9_unsigned_9; + + \c$vec_4\ <= (Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(Prop1_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop1_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$app_arg_3_5\ <= (\c$vec_4\(0 to 1-1),\c$vec_4\(1 to \c$vec_4\'high)); + + \c$app_arg_3\ <= \c$app_arg_3_5\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_1 <= result_10.Tup10_sel6_unsigned_6; + + tm2_1 <= result_10.Tup10_sel7_unsigned_7; + + mm1_1 <= result_10.Tup10_sel4_unsigned_4; + + mm2_1 <= result_10.Tup10_sel5_unsigned_5; + + ff1_1 <= result_10.Tup10_sel2_unsigned_2; + + ff2_1 <= result_10.Tup10_sel3_unsigned_3; + + tt1_1 <= result_10.Tup10_sel0_unsigned_0; + + tt2_1 <= result_10.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_3\(vec_index_1); + end block; + -- index end + + result_9 <= ( Tup2_sel0_array_of_signed_2 => Prop1_topEntity_types.array_of_signed_2'(0 => \c$case_alt_9\) + , Tup2_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_4_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_4\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_4\ <= result_11.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_0_sel1_Tup10; + + result_11 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_4\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_4\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (inp1 or inp1)) or ((opcode_1 = to_unsigned(1,1)) and inp1); + + ds4_1 <= \c$ds_app_arg_4\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_4\.Tup3_sel2_Tup10_1; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/Prop2_testBench_types.vhdl b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/Prop2_testBench_types.vhdl new file mode 100644 index 0000000..4e91837 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/Prop2_testBench_types.vhdl @@ -0,0 +1,244 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop2_testBench_types is + subtype index_17 is unsigned(4 downto 0); + subtype index_16 is unsigned(3 downto 0); + + + subtype rst_System is std_logic; + type array_of_boolean is array (integer range <>) of boolean; + subtype index_57 is unsigned(5 downto 0); + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + subtype index_29 is unsigned(4 downto 0); + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 11); + Tup2_1_sel1_boolean : boolean; + end record; + type Tup2_3 is record + Tup2_3_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 11); + Tup2_3_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_2 is record + Tup2_2_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_2_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (value : array_of_boolean) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_boolean; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (p : Tup2_3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_3; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; +end; + +package body Prop2_testBench_types is + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (value : array_of_boolean) return std_logic_vector is + alias ivalue : array_of_boolean(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 1); + begin + for i in ivalue'range loop + result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_boolean is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_boolean(0 to slv'length / 1 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 1 to (i+1) * 1 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 24))); + end; + function toSLV (p : Tup2_3) return std_logic_vector is + begin + return (toSLV(p.Tup2_3_sel0_array_of_signed_2_0) & toSLV(p.Tup2_3_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 25))); + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_array_of_signed_2_0) & toSLV(p.Tup2_2_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/clash-manifest.json new file mode 100644 index 0000000..d47ae3e --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/clash-manifest.json @@ -0,0 +1,63 @@ +{ + "components": [ + "testBench" + ], + "flags": [ + 20, + 20 + ], + "hash": "eb15b6de257319d3e7fd1404545539b14e5fabe2ac9bc630db955b7db80abdcc", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "Prop2_testBench_types.vhdl", + "sha256": "58a9d91ed7dcc593f26a1e8df0d54575d20930d181e026b4e2d919eff89d343e" + }, + { + "name": "testBench.vhdl", + "sha256": "99554d7603e496c971770e8df1451dcf21d19517415587e9f36acb79164daa51" + }, + { + "name": "testBench_slv2string_FD7FE0FDE5409B5E.vhdl", + "sha256": "76ad6e6a41f26803fce0edeea54f88c878437b1a39bfb81fff18923737be7966" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "testBench" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench.vhdl b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench.vhdl new file mode 100644 index 0000000..ed07812 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench.vhdl @@ -0,0 +1,968 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop2_testBench_types.all; +use testBench_slv2string_FD7FE0FDE5409B5E.all; + +entity testBench is + port(result : out boolean); +end; + +architecture structural of testBench is + signal \c$ds_app_arg\ : Prop2_testBench_types.index_16; + signal \c$ds_app_arg_0\ : boolean; + signal s : Prop2_testBench_types.index_16 := to_unsigned(0,4); + -- prop2.hs:36:5-7 + signal \Prop2.testBench_clk\ : Prop2_testBench_types.clk_System; + signal z : Prop2_testBench_types.index_57; + signal result_1 : Prop2_testBench_types.index_29; + signal \c$ds_app_arg_1\ : boolean; + signal \c$result_rec\ : boolean; + signal s_0 : Prop2_testBench_types.index_29 := to_unsigned(0,5); + signal f2 : boolean; + signal \f'\ : boolean := false; + -- prop2.hs:10:1-43 + signal \c$ds_app_arg_2\ : Prop2_testBench_types.array_of_signed_2(0 to 0) := Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_2 : boolean; + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_3 : Prop2_testBench_types.Tup2; + -- prop2.hs:12:1-124 + signal \c$ds_app_arg_3\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_4 : Prop2_testBench_types.Tup10; + signal result_5 : Prop2_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop2_testBench_types.Tup10; + -- prop2.hs:8:1-76 + signal \c$ds_app_arg_4\ : Prop2_testBench_types.array_of_signed_2(0 to 11) := Prop2_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_6 : boolean; + signal \c$app_arg_1\ : Prop2_testBench_types.array_of_signed_2(0 to 11); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_7 : Prop2_testBench_types.Tup2_1; + -- prop2.hs:16:1-124 + signal \c$ds_app_arg_5\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(11,5) +, Tup10_sel7_unsigned_7 => to_unsigned(11,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(7,5) +, Tup10_sel3_unsigned_3 => to_unsigned(11,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_8 : Prop2_testBench_types.Tup10; + signal result_9 : Prop2_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop2_testBench_types.Tup10; + -- prop2.hs:8:1-76 + signal \c$ds_app_arg_6\ : Prop2_testBench_types.array_of_signed_2(0 to 11) := Prop2_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_10 : boolean; + signal \c$app_arg_3\ : Prop2_testBench_types.array_of_signed_2(0 to 11); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_11 : Prop2_testBench_types.Tup2_1; + -- prop2.hs:14:1-125 + signal \c$ds_app_arg_7\ : Prop2_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_12 : Prop2_testBench_types.Tup10; + signal result_13 : Prop2_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop2_testBench_types.Tup10; + signal \c$ds_app_arg_8\ : Prop2_testBench_types.index_17; + signal \c$ds_app_arg_9\ : boolean; + signal s_1 : Prop2_testBench_types.index_17 := to_unsigned(0,5); + -- prop2.hs:29:1-9 + signal \c$Prop2.testBench_app_arg\ : Prop2_testBench_types.rst_System; + signal \c$ds_app_arg_selection_res\ : boolean; + signal \c$vec\ : Prop2_testBench_types.array_of_boolean(0 to 15); + signal result_selection_res : boolean; + signal \c$vec_0\ : Prop2_testBench_types.array_of_boolean(0 to 28); + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec_1\ : Prop2_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop2_testBench_types.Tup2_2; + signal \c$vec_2\ : Prop2_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop2_testBench_types.Tup2_2; + signal ds4_selection_res : boolean; + signal \c$vec_3\ : Prop2_testBench_types.array_of_signed_2(0 to 12); + signal \c$app_arg_1_1\ : Prop2_testBench_types.Tup2_3; + signal \c$vec_4\ : Prop2_testBench_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_0 : boolean; + signal \c$vec_5\ : Prop2_testBench_types.array_of_signed_2(0 to 12); + signal \c$app_arg_3_3\ : Prop2_testBench_types.Tup2_3; + signal \c$vec_6\ : Prop2_testBench_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_1 : boolean; + signal \c$ds_app_arg_selection_res_0\ : boolean; + signal \c$vec_7\ : Prop2_testBench_types.array_of_boolean(0 to 16); + +begin + \c$ds_app_arg_selection_res\ <= s < to_unsigned(15,4); + + \c$ds_app_arg\ <= s + to_unsigned(1,4) when \c$ds_app_arg_selection_res\ else + s; + + \c$vec\ <= Prop2_testBench_types.array_of_boolean'( true + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false ); + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 16-1; + begin + vec_index <= to_integer((signed(std_logic_vector(resize(s,64))))) + -- pragma translate_off + mod 16 + -- pragma translate_on + ; + \c$ds_app_arg_0\ <= \c$vec\(vec_index); + end block; + -- index end + + -- register begin + s_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + s <= to_unsigned(0,4); + elsif rising_edge(\Prop2.testBench_clk\) then + s <= \c$ds_app_arg\; + end if; + end process; + -- register end + + -- tbClockGen begin + -- pragma translate_off + clkGen : process is + constant half_periodH : time := 10000000 fs / 2; + constant half_periodL : time := 10000000 fs - half_periodH; + begin + \Prop2.testBench_clk\ <= '0'; + wait for 10000 ps; + while (not \c$result_rec\) loop + \Prop2.testBench_clk\ <= not \Prop2.testBench_clk\; + wait for half_periodH; + \Prop2.testBench_clk\ <= not \Prop2.testBench_clk\; + wait for half_periodL; + end loop; + wait; + end process; + -- pragma translate_on + -- tbClockGen end + + z <= resize(s_0,6) + resize(to_unsigned(1,5),6); + + result_selection_res <= z > to_unsigned(28,6); + + result_1 <= to_unsigned(28,5) when result_selection_res else + resize(z,5); + + \c$vec_0\ <= Prop2_testBench_types.array_of_boolean'( false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true ); + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 29-1; + begin + vec_index_0 <= to_integer((signed(std_logic_vector(resize(s_0,64))))) + -- pragma translate_off + mod 29 + -- pragma translate_on + ; + \c$ds_app_arg_1\ <= \c$vec_0\(vec_index_0); + end block; + -- index end + + \c$result_rec\ <= \f'\ when \f'\ else + f2; + + -- register begin + s_0_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + s_0 <= to_unsigned(0,5); + elsif rising_edge(\Prop2.testBench_clk\) then + s_0 <= result_1; + end if; + end process; + -- register end + + -- assert begin + r_assert : block + -- pragma translate_off + signal actual : boolean; + signal expected : boolean; + -- pragma translate_on + begin + -- pragma translate_off + actual <= result_2; + expected <= \c$ds_app_arg_1\; + process(\Prop2.testBench_clk\) is + begin + if (rising_edge(\Prop2.testBench_clk\)) then + assert (toSLV(actual) = toSLV(expected)) report (("outputVerifier") & ", expected: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(expected)) & ", actual: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(actual))) severity error; + end if; + end process; + -- pragma translate_on + f2 <= \f'\; + end block; + -- assert end + + -- register begin + f_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \f'\ <= false; + elsif rising_edge(\Prop2.testBench_clk\) then + \f'\ <= (s_0 = to_unsigned(28,5)); + end if; + end process; + -- register end + + -- register begin + cds_app_arg_2_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_2\ <= Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_2\ <= result_3.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec_1\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1 <= result_4.Tup10_sel8_unsigned_8; + + fm2 <= result_4.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$app_arg_7\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_4.Tup10_sel6_unsigned_6; + + tm2 <= result_4.Tup10_sel7_unsigned_7; + + mm1 <= result_4.Tup10_sel4_unsigned_4; + + mm2 <= result_4.Tup10_sel5_unsigned_5; + + ff1 <= result_4.Tup10_sel2_unsigned_2; + + ff2 <= result_4.Tup10_sel3_unsigned_3; + + tt1 <= result_4.Tup10_sel0_unsigned_0; + + tt2 <= result_4.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg_2\(vec_index_1); + end block; + -- index end + + result_3 <= ( Tup2_sel0_array_of_signed_2 => Prop2_testBench_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_3_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_3\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_3\ <= result_5.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_0_sel1_Tup10; + + result_5 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_3\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_3\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_10 or result_6)) or ((opcode = to_unsigned(1,1)) and result_10); + + ds4 <= \c$ds_app_arg_3\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_3\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_4_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_4\ <= Prop2_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_4\ <= result_7.Tup2_1_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_1_sel1_boolean; + + \c$vec_3\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$app_arg_1_1\ <= (\c$vec_3\(0 to 12-1),\c$vec_3\(12 to \c$vec_3\'high)); + + \c$vec_4\ <= \c$app_arg_1_1\.Tup2_3_sel0_array_of_signed_2_0; + + -- imap begin + imap : block + function max (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_0 : for i in \c$app_arg_1\'range generate + begin + fun_1 : block + signal \c$app_arg_8\ : signed(63 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_9\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + begin + \c$app_arg_1\(i) <= \c$case_alt_7\; + + \c$app_arg_8\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_4\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tt2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tt1_1); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_5\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= ff2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= ff1_1); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_9\; + + \c$case_alt_selection_res_6\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= mm2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= mm1_1); + + \c$case_alt_9\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_7\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tm1_1) and \c$app_arg_9\); + + \c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_8\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= fm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= fm1_1) and \c$app_arg_9\); + + \c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$vec_4\(i); + + fm1_1 <= result_8.Tup10_sel8_unsigned_8; + + fm2_1 <= result_8.Tup10_sel9_unsigned_9; + + \c$app_arg_9\ <= \c$vec_4\(i) = to_signed(0,2); + + tm1_1 <= result_8.Tup10_sel6_unsigned_6; + + tm2_1 <= result_8.Tup10_sel7_unsigned_7; + + mm1_1 <= result_8.Tup10_sel4_unsigned_4; + + mm2_1 <= result_8.Tup10_sel5_unsigned_5; + + ff1_1 <= result_8.Tup10_sel2_unsigned_2; + + ff2_1 <= result_8.Tup10_sel3_unsigned_3; + + tt1_1 <= result_8.Tup10_sel0_unsigned_0; + + tt2_1 <= result_8.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 12-1; + begin + vec_index_2 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_4\(vec_index_2); + end block; + -- index end + + result_7 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_1\ + , Tup2_1_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_5_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_5\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(11,5) + , Tup10_sel7_unsigned_7 => to_unsigned(11,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(7,5) + , Tup10_sel3_unsigned_3 => to_unsigned(11,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_5\ <= result_9.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_0_sel1_Tup10; + + result_9 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_5\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_5\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (\c$ds_app_arg_9\ or \c$ds_app_arg_9\)) or ((opcode_0 = to_unsigned(1,1)) and \c$ds_app_arg_9\); + + ds4_0 <= \c$ds_app_arg_5\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_5\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_6_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_6\ <= Prop2_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_6\ <= result_11.Tup2_1_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_1_sel1_boolean; + + \c$vec_5\ <= (Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(Prop2_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$app_arg_3_3\ <= (\c$vec_5\(0 to 12-1),\c$vec_5\(12 to \c$vec_5\'high)); + + \c$vec_6\ <= \c$app_arg_3_3\.Tup2_3_sel0_array_of_signed_2_0; + + -- imap begin + imap_1 : block + function max_0 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_2 : for i_0 in \c$app_arg_3\'range generate + begin + fun_2 : block + signal \c$app_arg_10\ : signed(63 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_11\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + begin + \c$app_arg_3\(i_0) <= \c$case_alt_12\; + + \c$app_arg_10\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tt2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tt1_2); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= ff2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= ff1_2); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_14\; + + \c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= mm2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= mm1_2); + + \c$case_alt_14\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tm1_2) and \c$app_arg_11\); + + \c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= fm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= fm1_2) and \c$app_arg_11\); + + \c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$vec_6\(i_0); + + fm1_2 <= result_12.Tup10_sel8_unsigned_8; + + fm2_2 <= result_12.Tup10_sel9_unsigned_9; + + \c$app_arg_11\ <= \c$vec_6\(i_0) = to_signed(0,2); + + tm1_2 <= result_12.Tup10_sel6_unsigned_6; + + tm2_2 <= result_12.Tup10_sel7_unsigned_7; + + mm1_2 <= result_12.Tup10_sel4_unsigned_4; + + mm2_2 <= result_12.Tup10_sel5_unsigned_5; + + ff1_2 <= result_12.Tup10_sel2_unsigned_2; + + ff2_2 <= result_12.Tup10_sel3_unsigned_3; + + tt1_2 <= result_12.Tup10_sel0_unsigned_0; + + tt2_2 <= result_12.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_3 : block + signal vec_index_3 : integer range 0 to 12-1; + begin + vec_index_3 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_6\(vec_index_3); + end block; + -- index end + + result_11 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_3\ + , Tup2_1_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_7_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + \c$ds_app_arg_7\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop2.testBench_clk\) then + \c$ds_app_arg_7\ <= result_13.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_12 <= result_13.Tup2_0_sel1_Tup10; + + result_13 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_7\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_7\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_0\)) or ((opcode_1 = to_unsigned(1,1)) and \c$ds_app_arg_0\); + + ds4_1 <= \c$ds_app_arg_7\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_7\.Tup3_sel2_Tup10_1; + + \c$ds_app_arg_selection_res_0\ <= s_1 < to_unsigned(16,5); + + \c$ds_app_arg_8\ <= s_1 + to_unsigned(1,5) when \c$ds_app_arg_selection_res_0\ else + s_1; + + \c$vec_7\ <= Prop2_testBench_types.array_of_boolean'( false + , false + , false + , false + , false + , false + , false + , true + , true + , true + , true + , true + , true + , true + , false + , false + , false ); + + -- index begin + indexVec_4 : block + signal vec_index_4 : integer range 0 to 17-1; + begin + vec_index_4 <= to_integer((signed(std_logic_vector(resize(s_1,64))))) + -- pragma translate_off + mod 17 + -- pragma translate_on + ; + \c$ds_app_arg_9\ <= \c$vec_7\(vec_index_4); + end block; + -- index end + + -- register begin + s_1_register : process(\Prop2.testBench_clk\,\c$Prop2.testBench_app_arg\) + begin + if \c$Prop2.testBench_app_arg\ = '1' then + s_1 <= to_unsigned(0,5); + elsif rising_edge(\Prop2.testBench_clk\) then + s_1 <= \c$ds_app_arg_8\; + end if; + end process; + -- register end + + -- resetGen begin + resetGen : block + constant reset_delay : time := 10000 ps - 1 ps + (integer'(1) * 10000 ps); + begin + -- pragma translate_off + \c$Prop2.testBench_app_arg\ + <= '1', + '0' after reset_delay; + -- pragma translate_on + end block; + -- resetGen end + + result <= \c$result_rec\; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl new file mode 100644 index 0000000..dcabb4a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl @@ -0,0 +1,24 @@ +-- helper function of Clash.Explicit.Testbench.assert +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING; +end; + +package body testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING is + variable result : string (1 to slv'length); + variable res_l : string (1 to 3); + variable r : integer; + begin + r := 1; + for i in slv'range loop + res_l := std_logic'image(slv(i)); + result(r) := res_l(2); + r := r + 1; + end loop; + return result; + end slv2string; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/Prop2_topEntity_types.vhdl b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/Prop2_topEntity_types.vhdl new file mode 100644 index 0000000..04948e8 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/Prop2_topEntity_types.vhdl @@ -0,0 +1,235 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop2_topEntity_types is + + + type Tup2_2 is record + Tup2_2_sel0_boolean_0 : boolean; + Tup2_2_sel1_boolean_1 : boolean; + end record; + subtype rst_System is std_logic; + subtype en_System is boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 11); + Tup2_1_sel1_boolean : boolean; + end record; + type Tup2_4 is record + Tup2_4_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 11); + Tup2_4_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_3 is record + Tup2_3_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_3_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (p : Tup2_4) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_4; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_3; +end; + +package body Prop2_topEntity_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_boolean_0) & toSLV(p.Tup2_2_sel1_boolean_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1))); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 24))); + end; + function toSLV (p : Tup2_4) return std_logic_vector is + begin + return (toSLV(p.Tup2_4_sel0_array_of_signed_2_0) & toSLV(p.Tup2_4_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_4 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 23)),fromSLV(islv(24 to 25))); + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_3) return std_logic_vector is + begin + return (toSLV(p.Tup2_3_sel0_array_of_signed_2_0) & toSLV(p.Tup2_3_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/clash-manifest.json new file mode 100644 index 0000000..f95b8b8 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/clash-manifest.json @@ -0,0 +1,101 @@ +{ + "components": [ + "topEntity" + ], + "flags": [ + 20, + 20 + ], + "hash": "59f62714a88c79f828a8cf0a4706b822f68adef7ba09c0ec69b58be998929e30", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "topEntity.sdc", + "sha256": "13d4c1aafcc09a84d81d3b60d513cb901384a10e27e5a5a16572a600f15895f3" + }, + { + "name": "Prop2_topEntity_types.vhdl", + "sha256": "84a80db2831ec1988012b412544e8d2c1e644db78c58f80c405bf481b69f4c3f" + }, + { + "name": "topEntity.vhdl", + "sha256": "8fda13a2a546eeca6a28f12380bb59dd8653deca2c5b55305b9fc3c6a4a3ea56" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "clk", + "is_clock": true, + "type_name": "clk.Prop2_topEntity_types.clk_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "rst", + "is_clock": false, + "type_name": "rst.Prop2_topEntity_types.rst_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "en", + "is_clock": false, + "type_name": "en.Prop2_topEntity_types.en_System" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_0", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_1", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "topEntity" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.sdc b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.sdc new file mode 100644 index 0000000..885f86a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.sdc @@ -0,0 +1,2 @@ +create_clock -name {clk} -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] + diff --git a/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.vhdl b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.vhdl new file mode 100644 index 0000000..d278c5e --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop2/Prop2.topEntity/topEntity.vhdl @@ -0,0 +1,753 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop2_topEntity_types.all; + +entity topEntity is + port(-- clock + clk : in Prop2_topEntity_types.clk_System; + -- reset + rst : in Prop2_topEntity_types.rst_System; + -- enable + en : in Prop2_topEntity_types.en_System; + eta1_0 : in boolean; + eta1_1 : in boolean; + result : out boolean); +end; + +architecture structural of topEntity is + -- prop2.hs:18:1-206 + signal inp1 : boolean; + -- prop2.hs:18:1-206 + signal inp2 : boolean; + -- prop2.hs:10:1-43 + signal \c$ds_app_arg\ : Prop2_topEntity_types.array_of_signed_2(0 to 0) := Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_1 : Prop2_topEntity_types.Tup2; + -- prop2.hs:12:1-124 + signal \c$ds_app_arg_0\ : Prop2_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_2 : Prop2_topEntity_types.Tup10; + signal result_3 : Prop2_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop2_topEntity_types.Tup10; + -- prop2.hs:8:1-76 + signal \c$ds_app_arg_1\ : Prop2_topEntity_types.array_of_signed_2(0 to 11) := Prop2_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_4 : boolean; + signal \c$app_arg_1\ : Prop2_topEntity_types.array_of_signed_2(0 to 11); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_5 : Prop2_topEntity_types.Tup2_1; + -- prop2.hs:16:1-124 + signal \c$ds_app_arg_2\ : Prop2_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(11,5) +, Tup10_sel7_unsigned_7 => to_unsigned(11,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(7,5) +, Tup10_sel3_unsigned_3 => to_unsigned(11,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_6 : Prop2_topEntity_types.Tup10; + signal result_7 : Prop2_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop2_topEntity_types.Tup10; + -- prop2.hs:8:1-76 + signal \c$ds_app_arg_3\ : Prop2_topEntity_types.array_of_signed_2(0 to 11) := Prop2_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_8 : boolean; + signal \c$app_arg_3\ : Prop2_topEntity_types.array_of_signed_2(0 to 11); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_9 : Prop2_topEntity_types.Tup2_1; + -- prop2.hs:14:1-125 + signal \c$ds_app_arg_4\ : Prop2_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_10 : Prop2_topEntity_types.Tup10; + signal result_11 : Prop2_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop2_topEntity_types.Tup10; + signal eta1 : Prop2_topEntity_types.Tup2_2; + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec\ : Prop2_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop2_topEntity_types.Tup2_3; + signal \c$vec_0\ : Prop2_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop2_topEntity_types.Tup2_3; + signal ds4_selection_res : boolean; + signal \c$vec_1\ : Prop2_topEntity_types.array_of_signed_2(0 to 12); + signal \c$app_arg_1_1\ : Prop2_topEntity_types.Tup2_4; + signal \c$vec_2\ : Prop2_topEntity_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_0 : boolean; + signal \c$vec_3\ : Prop2_topEntity_types.array_of_signed_2(0 to 12); + signal \c$app_arg_3_3\ : Prop2_topEntity_types.Tup2_4; + signal \c$vec_4\ : Prop2_topEntity_types.array_of_signed_2(0 to 11); + signal ds4_selection_res_1 : boolean; + +begin + eta1 <= ( Tup2_2_sel0_boolean_0 => eta1_0 + , Tup2_2_sel1_boolean_1 => eta1_1 ); + + inp1 <= eta1.Tup2_2_sel0_boolean_0; + + inp2 <= eta1.Tup2_2_sel1_boolean_1; + + -- register begin + cds_app_arg_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg\ <= Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg\ <= result_1.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result <= result_1.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec\ <= (Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec\(0 to 1-1),\c$vec\(1 to \c$vec\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_3_sel0_array_of_signed_2_0(0); + + fm1 <= result_2.Tup10_sel8_unsigned_8; + + fm2 <= result_2.Tup10_sel9_unsigned_9; + + \c$vec_0\ <= (Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$app_arg_7\ <= (\c$vec_0\(0 to 1-1),\c$vec_0\(1 to \c$vec_0\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_3_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_2.Tup10_sel6_unsigned_6; + + tm2 <= result_2.Tup10_sel7_unsigned_7; + + mm1 <= result_2.Tup10_sel4_unsigned_4; + + mm2 <= result_2.Tup10_sel5_unsigned_5; + + ff1 <= result_2.Tup10_sel2_unsigned_2; + + ff2 <= result_2.Tup10_sel3_unsigned_3; + + tt1 <= result_2.Tup10_sel0_unsigned_0; + + tt2 <= result_2.Tup10_sel1_unsigned_1; + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 1-1; + begin + vec_index <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg\(vec_index); + end block; + -- index end + + result_1 <= ( Tup2_sel0_array_of_signed_2 => Prop2_topEntity_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_0_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_0\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_0\ <= result_3.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_0_sel1_Tup10; + + result_3 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_0\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_0\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_8 or result_4)) or ((opcode = to_unsigned(1,1)) and result_8); + + ds4 <= \c$ds_app_arg_0\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_0\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_1_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_1\ <= Prop2_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_1\ <= result_5.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_1_sel1_boolean; + + \c$vec_1\ <= (Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$app_arg_1_1\ <= (\c$vec_1\(0 to 12-1),\c$vec_1\(12 to \c$vec_1\'high)); + + \c$vec_2\ <= \c$app_arg_1_1\.Tup2_4_sel0_array_of_signed_2_0; + + -- imap begin + imap : block + function max (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_0 : for i in \c$app_arg_1\'range generate + begin + fun_1 : block + signal \c$app_arg_8\ : signed(63 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_9\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + begin + \c$app_arg_1\(i) <= \c$case_alt_7\; + + \c$app_arg_8\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_4\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tt2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tt1_1); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_5\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= ff2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= ff1_1); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_9\; + + \c$case_alt_selection_res_6\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= mm2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= mm1_1); + + \c$case_alt_9\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_7\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tm1_1) and \c$app_arg_9\); + + \c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_8\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= fm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= fm1_1) and \c$app_arg_9\); + + \c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$vec_2\(i); + + fm1_1 <= result_6.Tup10_sel8_unsigned_8; + + fm2_1 <= result_6.Tup10_sel9_unsigned_9; + + \c$app_arg_9\ <= \c$vec_2\(i) = to_signed(0,2); + + tm1_1 <= result_6.Tup10_sel6_unsigned_6; + + tm2_1 <= result_6.Tup10_sel7_unsigned_7; + + mm1_1 <= result_6.Tup10_sel4_unsigned_4; + + mm2_1 <= result_6.Tup10_sel5_unsigned_5; + + ff1_1 <= result_6.Tup10_sel2_unsigned_2; + + ff2_1 <= result_6.Tup10_sel3_unsigned_3; + + tt1_1 <= result_6.Tup10_sel0_unsigned_0; + + tt2_1 <= result_6.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 12-1; + begin + vec_index_0 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_1\(vec_index_0); + end block; + -- index end + + result_5 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_1\ + , Tup2_1_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_2_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_2\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(11,5) + , Tup10_sel7_unsigned_7 => to_unsigned(11,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(7,5) + , Tup10_sel3_unsigned_3 => to_unsigned(11,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_2\ <= result_7.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_0_sel1_Tup10; + + result_7 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_2\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_2\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (inp2 or inp2)) or ((opcode_0 = to_unsigned(1,1)) and inp2); + + ds4_0 <= \c$ds_app_arg_2\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_2\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_3_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_3\ <= Prop2_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_3\ <= result_9.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_1_sel1_boolean; + + \c$vec_3\ <= (Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(Prop2_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop2_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$app_arg_3_3\ <= (\c$vec_3\(0 to 12-1),\c$vec_3\(12 to \c$vec_3\'high)); + + \c$vec_4\ <= \c$app_arg_3_3\.Tup2_4_sel0_array_of_signed_2_0; + + -- imap begin + imap_1 : block + function max_0 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_2 : for i_0 in \c$app_arg_3\'range generate + begin + fun_2 : block + signal \c$app_arg_10\ : signed(63 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_11\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + begin + \c$app_arg_3\(i_0) <= \c$case_alt_12\; + + \c$app_arg_10\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(12)))))),64))); + + \c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tt2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tt1_2); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= ff2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= ff1_2); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_14\; + + \c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= mm2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= mm1_2); + + \c$case_alt_14\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tm1_2) and \c$app_arg_11\); + + \c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= fm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= fm1_2) and \c$app_arg_11\); + + \c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$vec_4\(i_0); + + fm1_2 <= result_10.Tup10_sel8_unsigned_8; + + fm2_2 <= result_10.Tup10_sel9_unsigned_9; + + \c$app_arg_11\ <= \c$vec_4\(i_0) = to_signed(0,2); + + tm1_2 <= result_10.Tup10_sel6_unsigned_6; + + tm2_2 <= result_10.Tup10_sel7_unsigned_7; + + mm1_2 <= result_10.Tup10_sel4_unsigned_4; + + mm2_2 <= result_10.Tup10_sel5_unsigned_5; + + ff1_2 <= result_10.Tup10_sel2_unsigned_2; + + ff2_2 <= result_10.Tup10_sel3_unsigned_3; + + tt1_2 <= result_10.Tup10_sel0_unsigned_0; + + tt2_2 <= result_10.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 12-1; + begin + vec_index_1 <= to_integer(to_signed(11,64)) + -- pragma translate_off + mod 12 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_3\(vec_index_1); + end block; + -- index end + + result_9 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_3\ + , Tup2_1_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_4_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_4\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_4\ <= result_11.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_0_sel1_Tup10; + + result_11 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_4\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_4\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (inp1 or inp1)) or ((opcode_1 = to_unsigned(1,1)) and inp1); + + ds4_1 <= \c$ds_app_arg_4\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_4\.Tup3_sel2_Tup10_1; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/Prop3_testBench_types.vhdl b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/Prop3_testBench_types.vhdl new file mode 100644 index 0000000..dbff778 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/Prop3_testBench_types.vhdl @@ -0,0 +1,213 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop3_testBench_types is + subtype index_33 is unsigned(5 downto 0); + subtype index_17 is unsigned(4 downto 0); + subtype index_16 is unsigned(3 downto 0); + + + subtype rst_System is std_logic; + type array_of_boolean is array (integer range <>) of boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_1_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (value : array_of_boolean) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_boolean; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; +end; + +package body Prop3_testBench_types is + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (value : array_of_boolean) return std_logic_vector is + alias ivalue : array_of_boolean(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 1); + begin + for i in ivalue'range loop + result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_boolean is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_boolean(0 to slv'length / 1 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 1 to (i+1) * 1 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2_0) & toSLV(p.Tup2_1_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/clash-manifest.json new file mode 100644 index 0000000..8285ebc --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/clash-manifest.json @@ -0,0 +1,63 @@ +{ + "components": [ + "testBench" + ], + "flags": [ + 20, + 20 + ], + "hash": "cfcab95863eef5c32ad8f1cdd6fe42394cc0cb4e86bbaa819c3ccf6e4093d483", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "Prop3_testBench_types.vhdl", + "sha256": "11236b5d403deb624a5e9bccec7e6ece64f410f2a928d435b2a43e6d5d5e3714" + }, + { + "name": "testBench.vhdl", + "sha256": "ed0c45c2b5df3fb62b9b2be90e06ace7883b0537616f50a015b5106263d0351b" + }, + { + "name": "testBench_slv2string_FD7FE0FDE5409B5E.vhdl", + "sha256": "76ad6e6a41f26803fce0edeea54f88c878437b1a39bfb81fff18923737be7966" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "testBench" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench.vhdl b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench.vhdl new file mode 100644 index 0000000..93d8fbf --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench.vhdl @@ -0,0 +1,1073 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop3_testBench_types.all; +use testBench_slv2string_FD7FE0FDE5409B5E.all; + +entity testBench is + port(result : out boolean); +end; + +architecture structural of testBench is + signal \c$ds_app_arg\ : Prop3_testBench_types.index_16; + signal \c$ds_app_arg_0\ : boolean; + signal s : Prop3_testBench_types.index_16 := to_unsigned(0,4); + -- prop3.hs:37:5-7 + signal \Prop3.testBench_clk\ : Prop3_testBench_types.clk_System; + signal z : Prop3_testBench_types.index_33; + signal result_1 : Prop3_testBench_types.index_17; + signal \c$ds_app_arg_1\ : boolean; + signal \c$result_rec\ : boolean; + signal s_0 : Prop3_testBench_types.index_17 := to_unsigned(0,5); + signal f2 : boolean; + signal \f'\ : boolean := false; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_2\ : Prop3_testBench_types.array_of_signed_2(0 to 0) := Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_2 : boolean; + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_3 : Prop3_testBench_types.Tup2; + -- prop3.hs:13:1-124 + signal \c$ds_app_arg_3\ : Prop3_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_4 : Prop3_testBench_types.Tup10; + signal result_5 : Prop3_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop3_testBench_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_4\ : Prop3_testBench_types.array_of_signed_2(0 to 0) := Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_6 : boolean; + signal \c$case_alt_4\ : signed(1 downto 0); + signal \c$case_alt_5\ : signed(1 downto 0); + signal \c$case_alt_6\ : signed(1 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_0 : unsigned(4 downto 0); + signal \c$app_arg_1\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_0 : unsigned(4 downto 0); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_7 : Prop3_testBench_types.Tup2; + -- prop3.hs:17:1-122 + signal \c$ds_app_arg_5\ : Prop3_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) +, Tup10_sel1_unsigned_1 => to_unsigned(1,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(1,5) +, Tup10_sel3_unsigned_3 => to_unsigned(1,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_8 : Prop3_testBench_types.Tup10; + signal result_9 : Prop3_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop3_testBench_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_6\ : Prop3_testBench_types.array_of_signed_2(0 to 0) := Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_10 : boolean; + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_3\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_11 : Prop3_testBench_types.Tup2; + -- prop3.hs:13:1-124 + signal \c$ds_app_arg_7\ : Prop3_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_12 : Prop3_testBench_types.Tup10; + signal result_13 : Prop3_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop3_testBench_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_8\ : Prop3_testBench_types.array_of_signed_2(0 to 0) := Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_14 : boolean; + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + signal \c$case_alt_17\ : signed(1 downto 0); + signal \c$case_alt_18\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_5\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$app_arg_6\ : signed(1 downto 0); + signal result_15 : Prop3_testBench_types.Tup2; + -- prop3.hs:15:1-125 + signal \c$ds_app_arg_9\ : Prop3_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_16 : Prop3_testBench_types.Tup10; + signal result_17 : Prop3_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_2 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_2 : Prop3_testBench_types.Tup10; + signal \c$ds_app_arg_10\ : Prop3_testBench_types.index_17; + signal \c$ds_app_arg_11\ : boolean; + signal s_1 : Prop3_testBench_types.index_17 := to_unsigned(0,5); + -- prop3.hs:30:1-9 + signal \c$Prop3.testBench_app_arg\ : Prop3_testBench_types.rst_System; + signal \c$ds_app_arg_selection_res\ : boolean; + signal \c$vec\ : Prop3_testBench_types.array_of_boolean(0 to 15); + signal result_selection_res : boolean; + signal \c$vec_0\ : Prop3_testBench_types.array_of_boolean(0 to 16); + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec_1\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop3_testBench_types.Tup2_1; + signal \c$vec_2\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_9\ : Prop3_testBench_types.Tup2_1; + signal ds4_selection_res : boolean; + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + signal \c$vec_3\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_21\ : Prop3_testBench_types.Tup2_1; + signal \c$vec_4\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_1_2\ : Prop3_testBench_types.Tup2_1; + signal ds4_selection_res_0 : boolean; + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + signal \c$vec_5\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_33\ : Prop3_testBench_types.Tup2_1; + signal \c$vec_6\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_3_5\ : Prop3_testBench_types.Tup2_1; + signal ds4_selection_res_1 : boolean; + signal \c$case_alt_selection_res_14\ : boolean; + signal \c$case_alt_selection_res_15\ : boolean; + signal \c$case_alt_selection_res_16\ : boolean; + signal \c$case_alt_selection_res_17\ : boolean; + signal \c$case_alt_selection_res_18\ : boolean; + signal \c$vec_7\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_45\ : Prop3_testBench_types.Tup2_1; + signal \c$vec_8\ : Prop3_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_5_8\ : Prop3_testBench_types.Tup2_1; + signal ds4_selection_res_2 : boolean; + signal \c$ds_app_arg_selection_res_0\ : boolean; + signal \c$vec_9\ : Prop3_testBench_types.array_of_boolean(0 to 16); + +begin + \c$ds_app_arg_selection_res\ <= s < to_unsigned(15,4); + + \c$ds_app_arg\ <= s + to_unsigned(1,4) when \c$ds_app_arg_selection_res\ else + s; + + \c$vec\ <= Prop3_testBench_types.array_of_boolean'( false + , false + , true + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false ); + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 16-1; + begin + vec_index <= to_integer((signed(std_logic_vector(resize(s,64))))) + -- pragma translate_off + mod 16 + -- pragma translate_on + ; + \c$ds_app_arg_0\ <= \c$vec\(vec_index); + end block; + -- index end + + -- register begin + s_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + s <= to_unsigned(0,4); + elsif rising_edge(\Prop3.testBench_clk\) then + s <= \c$ds_app_arg\; + end if; + end process; + -- register end + + -- tbClockGen begin + -- pragma translate_off + clkGen : process is + constant half_periodH : time := 10000000 fs / 2; + constant half_periodL : time := 10000000 fs - half_periodH; + begin + \Prop3.testBench_clk\ <= '0'; + wait for 10000 ps; + while (not \c$result_rec\) loop + \Prop3.testBench_clk\ <= not \Prop3.testBench_clk\; + wait for half_periodH; + \Prop3.testBench_clk\ <= not \Prop3.testBench_clk\; + wait for half_periodL; + end loop; + wait; + end process; + -- pragma translate_on + -- tbClockGen end + + z <= resize(s_0,6) + resize(to_unsigned(1,5),6); + + result_selection_res <= z > to_unsigned(16,6); + + result_1 <= to_unsigned(16,5) when result_selection_res else + resize(z,5); + + \c$vec_0\ <= Prop3_testBench_types.array_of_boolean'( false + , false + , true + , true + , false + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true + , true ); + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 17-1; + begin + vec_index_0 <= to_integer((signed(std_logic_vector(resize(s_0,64))))) + -- pragma translate_off + mod 17 + -- pragma translate_on + ; + \c$ds_app_arg_1\ <= \c$vec_0\(vec_index_0); + end block; + -- index end + + \c$result_rec\ <= \f'\ when \f'\ else + f2; + + -- register begin + s_0_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + s_0 <= to_unsigned(0,5); + elsif rising_edge(\Prop3.testBench_clk\) then + s_0 <= result_1; + end if; + end process; + -- register end + + -- assert begin + r_assert : block + -- pragma translate_off + signal actual : boolean; + signal expected : boolean; + -- pragma translate_on + begin + -- pragma translate_off + actual <= result_2; + expected <= \c$ds_app_arg_1\; + process(\Prop3.testBench_clk\) is + begin + if (rising_edge(\Prop3.testBench_clk\)) then + assert (toSLV(actual) = toSLV(expected)) report (("outputVerifier") & ", expected: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(expected)) & ", actual: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(actual))) severity error; + end if; + end process; + -- pragma translate_on + f2 <= \f'\; + end block; + -- assert end + + -- register begin + f_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \f'\ <= false; + elsif rising_edge(\Prop3.testBench_clk\) then + \f'\ <= (s_0 = to_unsigned(16,5)); + end if; + end process; + -- register end + + -- register begin + cds_app_arg_2_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_2\ <= Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_2\ <= result_3.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec_1\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1 <= result_4.Tup10_sel8_unsigned_8; + + fm2 <= result_4.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$app_arg_9\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg\ <= \c$app_arg_9\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_4.Tup10_sel6_unsigned_6; + + tm2 <= result_4.Tup10_sel7_unsigned_7; + + mm1 <= result_4.Tup10_sel4_unsigned_4; + + mm2 <= result_4.Tup10_sel5_unsigned_5; + + ff1 <= result_4.Tup10_sel2_unsigned_2; + + ff2 <= result_4.Tup10_sel3_unsigned_3; + + tt1 <= result_4.Tup10_sel0_unsigned_0; + + tt2 <= result_4.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg_2\(vec_index_1); + end block; + -- index end + + result_3 <= ( Tup2_sel0_array_of_signed_2 => Prop3_testBench_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_3_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_3\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_3\ <= result_5.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_0_sel1_Tup10; + + result_5 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_3\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_3\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_14 or result_6)) or ((opcode = to_unsigned(1,1)) and result_14); + + ds4 <= \c$ds_app_arg_3\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_3\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_4_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_4\ <= Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_4\ <= result_7.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_sel1_boolean; + + \c$case_alt_selection_res_4\ <= (to_unsigned(0,5) <= tt2_0) and (to_unsigned(0,5) >= tt1_0); + + \c$case_alt_4\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_5\; + + \c$case_alt_selection_res_5\ <= (to_unsigned(0,5) <= ff2_0) and (to_unsigned(0,5) >= ff1_0); + + \c$case_alt_5\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_6\; + + \c$case_alt_selection_res_6\ <= (to_unsigned(0,5) <= mm2_0) and (to_unsigned(0,5) >= mm1_0); + + \c$case_alt_6\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_7\; + + \c$case_alt_selection_res_7\ <= (to_unsigned(0,5) <= tm2_0) and ((to_unsigned(0,5) >= tm1_0) and \c$app_arg_1\); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_8\ <= (to_unsigned(0,5) <= fm2_0) and ((to_unsigned(0,5) >= fm1_0) and \c$app_arg_1\); + + \c$vec_3\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$case_alt_sel_alt_21\ <= (\c$vec_3\(0 to 1-1),\c$vec_3\(1 to \c$vec_3\'high)); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$case_alt_sel_alt_21\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1_0 <= result_8.Tup10_sel8_unsigned_8; + + fm2_0 <= result_8.Tup10_sel9_unsigned_9; + + \c$vec_4\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$app_arg_1_2\ <= (\c$vec_4\(0 to 1-1),\c$vec_4\(1 to \c$vec_4\'high)); + + \c$app_arg_1\ <= \c$app_arg_1_2\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_0 <= result_8.Tup10_sel6_unsigned_6; + + tm2_0 <= result_8.Tup10_sel7_unsigned_7; + + mm1_0 <= result_8.Tup10_sel4_unsigned_4; + + mm2_0 <= result_8.Tup10_sel5_unsigned_5; + + ff1_0 <= result_8.Tup10_sel2_unsigned_2; + + ff2_0 <= result_8.Tup10_sel3_unsigned_3; + + tt1_0 <= result_8.Tup10_sel0_unsigned_0; + + tt2_0 <= result_8.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 1-1; + begin + vec_index_2 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_4\(vec_index_2); + end block; + -- index end + + result_7 <= ( Tup2_sel0_array_of_signed_2 => Prop3_testBench_types.array_of_signed_2'(0 => \c$case_alt_4\) + , Tup2_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_5_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_5\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) + , Tup10_sel1_unsigned_1 => to_unsigned(1,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(1,5) + , Tup10_sel3_unsigned_3 => to_unsigned(1,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_5\ <= result_9.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_0_sel1_Tup10; + + result_9 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_5\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_5\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (result_10 or result_10)) or ((opcode_0 = to_unsigned(1,1)) and result_10); + + ds4_0 <= \c$ds_app_arg_5\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_5\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_6_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_6\ <= Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_6\ <= result_11.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_sel1_boolean; + + \c$case_alt_selection_res_9\ <= (to_unsigned(0,5) <= tt2_1) and (to_unsigned(0,5) >= tt1_1); + + \c$case_alt_9\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_10\ <= (to_unsigned(0,5) <= ff2_1) and (to_unsigned(0,5) >= ff1_1); + + \c$case_alt_10\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_11\ <= (to_unsigned(0,5) <= mm2_1) and (to_unsigned(0,5) >= mm1_1); + + \c$case_alt_11\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_12\; + + \c$case_alt_selection_res_12\ <= (to_unsigned(0,5) <= tm2_1) and ((to_unsigned(0,5) >= tm1_1) and \c$app_arg_3\); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_13\ <= (to_unsigned(0,5) <= fm2_1) and ((to_unsigned(0,5) >= fm1_1) and \c$app_arg_3\); + + \c$vec_5\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$case_alt_sel_alt_33\ <= (\c$vec_5\(0 to 1-1),\c$vec_5\(1 to \c$vec_5\'high)); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$case_alt_sel_alt_33\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1_1 <= result_12.Tup10_sel8_unsigned_8; + + fm2_1 <= result_12.Tup10_sel9_unsigned_9; + + \c$vec_6\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$app_arg_3_5\ <= (\c$vec_6\(0 to 1-1),\c$vec_6\(1 to \c$vec_6\'high)); + + \c$app_arg_3\ <= \c$app_arg_3_5\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_1 <= result_12.Tup10_sel6_unsigned_6; + + tm2_1 <= result_12.Tup10_sel7_unsigned_7; + + mm1_1 <= result_12.Tup10_sel4_unsigned_4; + + mm2_1 <= result_12.Tup10_sel5_unsigned_5; + + ff1_1 <= result_12.Tup10_sel2_unsigned_2; + + ff2_1 <= result_12.Tup10_sel3_unsigned_3; + + tt1_1 <= result_12.Tup10_sel0_unsigned_0; + + tt2_1 <= result_12.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_3 : block + signal vec_index_3 : integer range 0 to 1-1; + begin + vec_index_3 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_6\(vec_index_3); + end block; + -- index end + + result_11 <= ( Tup2_sel0_array_of_signed_2 => Prop3_testBench_types.array_of_signed_2'(0 => \c$case_alt_9\) + , Tup2_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_7_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_7\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_7\ <= result_13.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_12 <= result_13.Tup2_0_sel1_Tup10; + + result_13 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_7\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_7\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_11\)) or ((opcode_1 = to_unsigned(1,1)) and \c$ds_app_arg_0\); + + ds4_1 <= \c$ds_app_arg_7\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_7\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_8_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_8\ <= Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_8\ <= result_15.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_14 <= result_15.Tup2_sel1_boolean; + + \c$case_alt_selection_res_14\ <= (to_unsigned(0,5) <= tt2_2) and (to_unsigned(0,5) >= tt1_2); + + \c$case_alt_14\ <= to_signed(1,2) when \c$case_alt_selection_res_14\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_15\ <= (to_unsigned(0,5) <= ff2_2) and (to_unsigned(0,5) >= ff1_2); + + \c$case_alt_15\ <= to_signed(-1,2) when \c$case_alt_selection_res_15\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_16\ <= (to_unsigned(0,5) <= mm2_2) and (to_unsigned(0,5) >= mm1_2); + + \c$case_alt_16\ <= to_signed(0,2) when \c$case_alt_selection_res_16\ else + \c$case_alt_17\; + + \c$case_alt_selection_res_17\ <= (to_unsigned(0,5) <= tm2_2) and ((to_unsigned(0,5) >= tm1_2) and \c$app_arg_5\); + + \c$case_alt_17\ <= to_signed(1,2) when \c$case_alt_selection_res_17\ else + \c$case_alt_18\; + + \c$case_alt_selection_res_18\ <= (to_unsigned(0,5) <= fm2_2) and ((to_unsigned(0,5) >= fm1_2) and \c$app_arg_5\); + + \c$vec_7\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_8\))); + + \c$case_alt_sel_alt_45\ <= (\c$vec_7\(0 to 1-1),\c$vec_7\(1 to \c$vec_7\'high)); + + \c$case_alt_18\ <= to_signed(-1,2) when \c$case_alt_selection_res_18\ else + \c$case_alt_sel_alt_45\.Tup2_1_sel0_array_of_signed_2_0(0); + + fm1_2 <= result_16.Tup10_sel8_unsigned_8; + + fm2_2 <= result_16.Tup10_sel9_unsigned_9; + + \c$vec_8\ <= (Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(Prop3_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_testBench_types.array_of_signed_2'(\c$ds_app_arg_8\))); + + \c$app_arg_5_8\ <= (\c$vec_8\(0 to 1-1),\c$vec_8\(1 to \c$vec_8\'high)); + + \c$app_arg_5\ <= \c$app_arg_5_8\.Tup2_1_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_2 <= result_16.Tup10_sel6_unsigned_6; + + tm2_2 <= result_16.Tup10_sel7_unsigned_7; + + mm1_2 <= result_16.Tup10_sel4_unsigned_4; + + mm2_2 <= result_16.Tup10_sel5_unsigned_5; + + ff1_2 <= result_16.Tup10_sel2_unsigned_2; + + ff2_2 <= result_16.Tup10_sel3_unsigned_3; + + tt1_2 <= result_16.Tup10_sel0_unsigned_0; + + tt2_2 <= result_16.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_4 : block + signal vec_index_4 : integer range 0 to 1-1; + begin + vec_index_4 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_6\ <= \c$ds_app_arg_8\(vec_index_4); + end block; + -- index end + + result_15 <= ( Tup2_sel0_array_of_signed_2 => Prop3_testBench_types.array_of_signed_2'(0 => \c$case_alt_14\) + , Tup2_sel1_boolean => \c$app_arg_6\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_9_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + \c$ds_app_arg_9\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop3.testBench_clk\) then + \c$ds_app_arg_9\ <= result_17.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_16 <= result_17.Tup2_0_sel1_Tup10; + + result_17 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_9\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_2.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_2.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_2.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_2.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_2.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_2.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_2.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_2.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_2.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_2.Tup10_sel9_unsigned_9 ) ); + + opcode_2 <= \c$ds_app_arg_9\.Tup3_sel0_unsigned; + + ds4_selection_res_2 <= ((opcode_2 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_0\)) or ((opcode_2 = to_unsigned(1,1)) and \c$ds_app_arg_0\); + + ds4_2 <= \c$ds_app_arg_9\.Tup3_sel1_Tup10_0 when ds4_selection_res_2 else + \c$ds_app_arg_9\.Tup3_sel2_Tup10_1; + + \c$ds_app_arg_selection_res_0\ <= s_1 < to_unsigned(16,5); + + \c$ds_app_arg_10\ <= s_1 + to_unsigned(1,5) when \c$ds_app_arg_selection_res_0\ else + s_1; + + \c$vec_9\ <= Prop3_testBench_types.array_of_boolean'( false + , false + , false + , false + , false + , false + , false + , true + , true + , true + , true + , true + , true + , true + , false + , false + , false ); + + -- index begin + indexVec_5 : block + signal vec_index_5 : integer range 0 to 17-1; + begin + vec_index_5 <= to_integer((signed(std_logic_vector(resize(s_1,64))))) + -- pragma translate_off + mod 17 + -- pragma translate_on + ; + \c$ds_app_arg_11\ <= \c$vec_9\(vec_index_5); + end block; + -- index end + + -- register begin + s_1_register : process(\Prop3.testBench_clk\,\c$Prop3.testBench_app_arg\) + begin + if \c$Prop3.testBench_app_arg\ = '1' then + s_1 <= to_unsigned(0,5); + elsif rising_edge(\Prop3.testBench_clk\) then + s_1 <= \c$ds_app_arg_10\; + end if; + end process; + -- register end + + -- resetGen begin + resetGen : block + constant reset_delay : time := 10000 ps - 1 ps + (integer'(1) * 10000 ps); + begin + -- pragma translate_off + \c$Prop3.testBench_app_arg\ + <= '1', + '0' after reset_delay; + -- pragma translate_on + end block; + -- resetGen end + + result <= \c$result_rec\; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl new file mode 100644 index 0000000..dcabb4a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl @@ -0,0 +1,24 @@ +-- helper function of Clash.Explicit.Testbench.assert +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING; +end; + +package body testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING is + variable result : string (1 to slv'length); + variable res_l : string (1 to 3); + variable r : integer; + begin + r := 1; + for i in slv'range loop + res_l := std_logic'image(slv(i)); + result(r) := res_l(2); + r := r + 1; + end loop; + return result; + end slv2string; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/Prop3_topEntity_types.vhdl b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/Prop3_topEntity_types.vhdl new file mode 100644 index 0000000..b3035c5 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/Prop3_topEntity_types.vhdl @@ -0,0 +1,205 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop3_topEntity_types is + + + type Tup2_1 is record + Tup2_1_sel0_boolean_0 : boolean; + Tup2_1_sel1_boolean_1 : boolean; + end record; + subtype rst_System is std_logic; + subtype en_System is boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_2 is record + Tup2_2_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_2_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; +end; + +package body Prop3_topEntity_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_boolean_0) & toSLV(p.Tup2_1_sel1_boolean_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1))); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_array_of_signed_2_0) & toSLV(p.Tup2_2_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/clash-manifest.json new file mode 100644 index 0000000..5d72d22 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/clash-manifest.json @@ -0,0 +1,101 @@ +{ + "components": [ + "topEntity" + ], + "flags": [ + 20, + 20 + ], + "hash": "2d4b8ae6a2d456b473f65a3711af4d3987763cf8729ff6c7af5c31a80eca9ce2", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "topEntity.sdc", + "sha256": "13d4c1aafcc09a84d81d3b60d513cb901384a10e27e5a5a16572a600f15895f3" + }, + { + "name": "Prop3_topEntity_types.vhdl", + "sha256": "cbcdfd88bc1a5fdb0722172278bd17151f26565660ce91e87982d1572a3ed71d" + }, + { + "name": "topEntity.vhdl", + "sha256": "18c64f888baae3e32a19d5ff2c25a0404a0f484fbcbe4b0ea2f7377df6ceef70" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "clk", + "is_clock": true, + "type_name": "clk.Prop3_topEntity_types.clk_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "rst", + "is_clock": false, + "type_name": "rst.Prop3_topEntity_types.rst_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "en", + "is_clock": false, + "type_name": "en.Prop3_topEntity_types.en_System" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_0", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_1", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "topEntity" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.sdc b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.sdc new file mode 100644 index 0000000..885f86a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.sdc @@ -0,0 +1,2 @@ +create_clock -name {clk} -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] + diff --git a/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.vhdl b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.vhdl new file mode 100644 index 0000000..539d459 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop3/Prop3.topEntity/topEntity.vhdl @@ -0,0 +1,878 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop3_topEntity_types.all; + +entity topEntity is + port(-- clock + clk : in Prop3_topEntity_types.clk_System; + -- reset + rst : in Prop3_topEntity_types.rst_System; + -- enable + en : in Prop3_topEntity_types.en_System; + eta1_0 : in boolean; + eta1_1 : in boolean; + result : out boolean); +end; + +architecture structural of topEntity is + -- prop3.hs:8:1-44 + signal \c$ds_app_arg\ : Prop3_topEntity_types.array_of_signed_2(0 to 0) := Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_1 : Prop3_topEntity_types.Tup2; + -- prop3.hs:13:1-124 + signal \c$ds_app_arg_0\ : Prop3_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_2 : Prop3_topEntity_types.Tup10; + signal result_3 : Prop3_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop3_topEntity_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_1\ : Prop3_topEntity_types.array_of_signed_2(0 to 0) := Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_4 : boolean; + signal \c$case_alt_4\ : signed(1 downto 0); + signal \c$case_alt_5\ : signed(1 downto 0); + signal \c$case_alt_6\ : signed(1 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_0 : unsigned(4 downto 0); + signal \c$app_arg_1\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_0 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_0 : unsigned(4 downto 0); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_5 : Prop3_topEntity_types.Tup2; + -- prop3.hs:17:1-122 + signal \c$ds_app_arg_2\ : Prop3_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) +, Tup10_sel1_unsigned_1 => to_unsigned(1,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(1,5) +, Tup10_sel3_unsigned_3 => to_unsigned(1,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_6 : Prop3_topEntity_types.Tup10; + signal result_7 : Prop3_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop3_topEntity_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_3\ : Prop3_topEntity_types.array_of_signed_2(0 to 0) := Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_8 : boolean; + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_3\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_9 : Prop3_topEntity_types.Tup2; + -- prop3.hs:13:1-124 + signal \c$ds_app_arg_4\ : Prop3_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_10 : Prop3_topEntity_types.Tup10; + signal result_11 : Prop3_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal input1 : boolean; + -- ProcessingElement.hs:9:1-777 + signal input2 : boolean; + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop3_topEntity_types.Tup10; + -- prop3.hs:8:1-44 + signal \c$ds_app_arg_5\ : Prop3_topEntity_types.array_of_signed_2(0 to 0) := Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_12 : boolean; + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + signal \c$case_alt_17\ : signed(1 downto 0); + signal \c$case_alt_18\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_5\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$app_arg_6\ : signed(1 downto 0); + signal result_13 : Prop3_topEntity_types.Tup2; + -- prop3.hs:15:1-125 + signal \c$ds_app_arg_6\ : Prop3_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_14 : Prop3_topEntity_types.Tup10; + signal result_15 : Prop3_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_2 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_2 : Prop3_topEntity_types.Tup10; + -- prop3.hs:19:1-332 + signal inp1 : boolean; + signal eta1 : Prop3_topEntity_types.Tup2_1; + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop3_topEntity_types.Tup2_2; + signal \c$vec_0\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_9\ : Prop3_topEntity_types.Tup2_2; + signal ds4_selection_res : boolean; + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + signal \c$vec_1\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_21\ : Prop3_topEntity_types.Tup2_2; + signal \c$vec_2\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_1_2\ : Prop3_topEntity_types.Tup2_2; + signal ds4_selection_res_0 : boolean; + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + signal \c$vec_3\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_33\ : Prop3_topEntity_types.Tup2_2; + signal \c$vec_4\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_3_5\ : Prop3_topEntity_types.Tup2_2; + signal ds4_selection_res_1 : boolean; + signal \c$case_alt_selection_res_14\ : boolean; + signal \c$case_alt_selection_res_15\ : boolean; + signal \c$case_alt_selection_res_16\ : boolean; + signal \c$case_alt_selection_res_17\ : boolean; + signal \c$case_alt_selection_res_18\ : boolean; + signal \c$vec_5\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_45\ : Prop3_topEntity_types.Tup2_2; + signal \c$vec_6\ : Prop3_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_5_8\ : Prop3_topEntity_types.Tup2_2; + signal ds4_selection_res_2 : boolean; + +begin + eta1 <= ( Tup2_1_sel0_boolean_0 => eta1_0 + , Tup2_1_sel1_boolean_1 => eta1_1 ); + + -- register begin + cds_app_arg_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg\ <= Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg\ <= result_1.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result <= result_1.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec\(0 to 1-1),\c$vec\(1 to \c$vec\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1 <= result_2.Tup10_sel8_unsigned_8; + + fm2 <= result_2.Tup10_sel9_unsigned_9; + + \c$vec_0\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$app_arg_9\ <= (\c$vec_0\(0 to 1-1),\c$vec_0\(1 to \c$vec_0\'high)); + + \c$app_arg\ <= \c$app_arg_9\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_2.Tup10_sel6_unsigned_6; + + tm2 <= result_2.Tup10_sel7_unsigned_7; + + mm1 <= result_2.Tup10_sel4_unsigned_4; + + mm2 <= result_2.Tup10_sel5_unsigned_5; + + ff1 <= result_2.Tup10_sel2_unsigned_2; + + ff2 <= result_2.Tup10_sel3_unsigned_3; + + tt1 <= result_2.Tup10_sel0_unsigned_0; + + tt2 <= result_2.Tup10_sel1_unsigned_1; + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 1-1; + begin + vec_index <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg\(vec_index); + end block; + -- index end + + result_1 <= ( Tup2_sel0_array_of_signed_2 => Prop3_topEntity_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_0_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_0\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_0\ <= result_3.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_0_sel1_Tup10; + + result_3 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_0\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_0\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_12 or result_4)) or ((opcode = to_unsigned(1,1)) and result_12); + + ds4 <= \c$ds_app_arg_0\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_0\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_1_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_1\ <= Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_1\ <= result_5.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_sel1_boolean; + + \c$case_alt_selection_res_4\ <= (to_unsigned(0,5) <= tt2_0) and (to_unsigned(0,5) >= tt1_0); + + \c$case_alt_4\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_5\; + + \c$case_alt_selection_res_5\ <= (to_unsigned(0,5) <= ff2_0) and (to_unsigned(0,5) >= ff1_0); + + \c$case_alt_5\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_6\; + + \c$case_alt_selection_res_6\ <= (to_unsigned(0,5) <= mm2_0) and (to_unsigned(0,5) >= mm1_0); + + \c$case_alt_6\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_7\; + + \c$case_alt_selection_res_7\ <= (to_unsigned(0,5) <= tm2_0) and ((to_unsigned(0,5) >= tm1_0) and \c$app_arg_1\); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_8\ <= (to_unsigned(0,5) <= fm2_0) and ((to_unsigned(0,5) >= fm1_0) and \c$app_arg_1\); + + \c$vec_1\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$case_alt_sel_alt_21\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$case_alt_sel_alt_21\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1_0 <= result_6.Tup10_sel8_unsigned_8; + + fm2_0 <= result_6.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$app_arg_1_2\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg_1\ <= \c$app_arg_1_2\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_0 <= result_6.Tup10_sel6_unsigned_6; + + tm2_0 <= result_6.Tup10_sel7_unsigned_7; + + mm1_0 <= result_6.Tup10_sel4_unsigned_4; + + mm2_0 <= result_6.Tup10_sel5_unsigned_5; + + ff1_0 <= result_6.Tup10_sel2_unsigned_2; + + ff2_0 <= result_6.Tup10_sel3_unsigned_3; + + tt1_0 <= result_6.Tup10_sel0_unsigned_0; + + tt2_0 <= result_6.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 1-1; + begin + vec_index_0 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_1\(vec_index_0); + end block; + -- index end + + result_5 <= ( Tup2_sel0_array_of_signed_2 => Prop3_topEntity_types.array_of_signed_2'(0 => \c$case_alt_4\) + , Tup2_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_2_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_2\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(1,5) + , Tup10_sel1_unsigned_1 => to_unsigned(1,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(1,5) + , Tup10_sel3_unsigned_3 => to_unsigned(1,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_2\ <= result_7.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_0_sel1_Tup10; + + result_7 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_2\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_2\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (result_8 or result_8)) or ((opcode_0 = to_unsigned(1,1)) and result_8); + + ds4_0 <= \c$ds_app_arg_2\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_2\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_3_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_3\ <= Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_3\ <= result_9.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_sel1_boolean; + + \c$case_alt_selection_res_9\ <= (to_unsigned(0,5) <= tt2_1) and (to_unsigned(0,5) >= tt1_1); + + \c$case_alt_9\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_10\ <= (to_unsigned(0,5) <= ff2_1) and (to_unsigned(0,5) >= ff1_1); + + \c$case_alt_10\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_11\ <= (to_unsigned(0,5) <= mm2_1) and (to_unsigned(0,5) >= mm1_1); + + \c$case_alt_11\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_12\; + + \c$case_alt_selection_res_12\ <= (to_unsigned(0,5) <= tm2_1) and ((to_unsigned(0,5) >= tm1_1) and \c$app_arg_3\); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_13\ <= (to_unsigned(0,5) <= fm2_1) and ((to_unsigned(0,5) >= fm1_1) and \c$app_arg_3\); + + \c$vec_3\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$case_alt_sel_alt_33\ <= (\c$vec_3\(0 to 1-1),\c$vec_3\(1 to \c$vec_3\'high)); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$case_alt_sel_alt_33\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1_1 <= result_10.Tup10_sel8_unsigned_8; + + fm2_1 <= result_10.Tup10_sel9_unsigned_9; + + \c$vec_4\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$app_arg_3_5\ <= (\c$vec_4\(0 to 1-1),\c$vec_4\(1 to \c$vec_4\'high)); + + \c$app_arg_3\ <= \c$app_arg_3_5\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_1 <= result_10.Tup10_sel6_unsigned_6; + + tm2_1 <= result_10.Tup10_sel7_unsigned_7; + + mm1_1 <= result_10.Tup10_sel4_unsigned_4; + + mm2_1 <= result_10.Tup10_sel5_unsigned_5; + + ff1_1 <= result_10.Tup10_sel2_unsigned_2; + + ff2_1 <= result_10.Tup10_sel3_unsigned_3; + + tt1_1 <= result_10.Tup10_sel0_unsigned_0; + + tt2_1 <= result_10.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_3\(vec_index_1); + end block; + -- index end + + result_9 <= ( Tup2_sel0_array_of_signed_2 => Prop3_topEntity_types.array_of_signed_2'(0 => \c$case_alt_9\) + , Tup2_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_4_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_4\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_4\ <= result_11.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_0_sel1_Tup10; + + result_11 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_4\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_4\.Tup3_sel0_unsigned; + + input1 <= eta1.Tup2_1_sel0_boolean_0; + + input2 <= eta1.Tup2_1_sel1_boolean_1; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (input1 or input2)) or ((opcode_1 = to_unsigned(1,1)) and input1); + + ds4_1 <= \c$ds_app_arg_4\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_4\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_5_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_5\ <= Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_5\ <= result_13.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_12 <= result_13.Tup2_sel1_boolean; + + \c$case_alt_selection_res_14\ <= (to_unsigned(0,5) <= tt2_2) and (to_unsigned(0,5) >= tt1_2); + + \c$case_alt_14\ <= to_signed(1,2) when \c$case_alt_selection_res_14\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_15\ <= (to_unsigned(0,5) <= ff2_2) and (to_unsigned(0,5) >= ff1_2); + + \c$case_alt_15\ <= to_signed(-1,2) when \c$case_alt_selection_res_15\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_16\ <= (to_unsigned(0,5) <= mm2_2) and (to_unsigned(0,5) >= mm1_2); + + \c$case_alt_16\ <= to_signed(0,2) when \c$case_alt_selection_res_16\ else + \c$case_alt_17\; + + \c$case_alt_selection_res_17\ <= (to_unsigned(0,5) <= tm2_2) and ((to_unsigned(0,5) >= tm1_2) and \c$app_arg_5\); + + \c$case_alt_17\ <= to_signed(1,2) when \c$case_alt_selection_res_17\ else + \c$case_alt_18\; + + \c$case_alt_selection_res_18\ <= (to_unsigned(0,5) <= fm2_2) and ((to_unsigned(0,5) >= fm1_2) and \c$app_arg_5\); + + \c$vec_5\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_5\))); + + \c$case_alt_sel_alt_45\ <= (\c$vec_5\(0 to 1-1),\c$vec_5\(1 to \c$vec_5\'high)); + + \c$case_alt_18\ <= to_signed(-1,2) when \c$case_alt_selection_res_18\ else + \c$case_alt_sel_alt_45\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1_2 <= result_14.Tup10_sel8_unsigned_8; + + fm2_2 <= result_14.Tup10_sel9_unsigned_9; + + \c$vec_6\ <= (Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(Prop3_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop3_topEntity_types.array_of_signed_2'(\c$ds_app_arg_5\))); + + \c$app_arg_5_8\ <= (\c$vec_6\(0 to 1-1),\c$vec_6\(1 to \c$vec_6\'high)); + + \c$app_arg_5\ <= \c$app_arg_5_8\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1_2 <= result_14.Tup10_sel6_unsigned_6; + + tm2_2 <= result_14.Tup10_sel7_unsigned_7; + + mm1_2 <= result_14.Tup10_sel4_unsigned_4; + + mm2_2 <= result_14.Tup10_sel5_unsigned_5; + + ff1_2 <= result_14.Tup10_sel2_unsigned_2; + + ff2_2 <= result_14.Tup10_sel3_unsigned_3; + + tt1_2 <= result_14.Tup10_sel0_unsigned_0; + + tt2_2 <= result_14.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 1-1; + begin + vec_index_2 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_6\ <= \c$ds_app_arg_5\(vec_index_2); + end block; + -- index end + + result_13 <= ( Tup2_sel0_array_of_signed_2 => Prop3_topEntity_types.array_of_signed_2'(0 => \c$case_alt_14\) + , Tup2_sel1_boolean => \c$app_arg_6\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_6_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_6\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_6\ <= result_15.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_14 <= result_15.Tup2_0_sel1_Tup10; + + result_15 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_6\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_2.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_2.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_2.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_2.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_2.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_2.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_2.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_2.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_2.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_2.Tup10_sel9_unsigned_9 ) ); + + opcode_2 <= \c$ds_app_arg_6\.Tup3_sel0_unsigned; + + ds4_selection_res_2 <= ((opcode_2 = to_unsigned(0,1)) and (inp1 or inp1)) or ((opcode_2 = to_unsigned(1,1)) and inp1); + + ds4_2 <= \c$ds_app_arg_6\.Tup3_sel1_Tup10_0 when ds4_selection_res_2 else + \c$ds_app_arg_6\.Tup3_sel2_Tup10_1; + + inp1 <= eta1.Tup2_1_sel0_boolean_0; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/Prop4_testBench_types.vhdl b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/Prop4_testBench_types.vhdl new file mode 100644 index 0000000..a0537a9 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/Prop4_testBench_types.vhdl @@ -0,0 +1,244 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop4_testBench_types is + subtype index_17 is unsigned(4 downto 0); + subtype index_16 is unsigned(3 downto 0); + + + subtype index_35 is unsigned(5 downto 0); + subtype index_18 is unsigned(4 downto 0); + subtype rst_System is std_logic; + type array_of_boolean is array (integer range <>) of boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 6); + Tup2_1_sel1_boolean : boolean; + end record; + type Tup2_3 is record + Tup2_3_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 6); + Tup2_3_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_2 is record + Tup2_2_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_2_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (value : array_of_boolean) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_boolean; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (p : Tup2_3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_3; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; +end; + +package body Prop4_testBench_types is + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (value : array_of_boolean) return std_logic_vector is + alias ivalue : array_of_boolean(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 1); + begin + for i in ivalue'range loop + result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_boolean is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_boolean(0 to slv'length / 1 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 1 to (i+1) * 1 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 14))); + end; + function toSLV (p : Tup2_3) return std_logic_vector is + begin + return (toSLV(p.Tup2_3_sel0_array_of_signed_2_0) & toSLV(p.Tup2_3_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 15))); + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_array_of_signed_2_0) & toSLV(p.Tup2_2_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/clash-manifest.json new file mode 100644 index 0000000..686a8e0 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/clash-manifest.json @@ -0,0 +1,63 @@ +{ + "components": [ + "testBench" + ], + "flags": [ + 20, + 20 + ], + "hash": "030081bc085c32ea869f87bbfb04bfad27365b453d70164fa62431e2f1becce9", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "Prop4_testBench_types.vhdl", + "sha256": "fba2b1070f653581f888ef1e63381e4b7893be54e9dc0d60e84ed3877ec1eece" + }, + { + "name": "testBench.vhdl", + "sha256": "0f7bdbc6b003aa8663eed0345d320f92c26d5b77e03d5aebd73a358efa025d5c" + }, + { + "name": "testBench_slv2string_FD7FE0FDE5409B5E.vhdl", + "sha256": "76ad6e6a41f26803fce0edeea54f88c878437b1a39bfb81fff18923737be7966" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "testBench" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench.vhdl b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench.vhdl new file mode 100644 index 0000000..b62468d --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench.vhdl @@ -0,0 +1,937 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop4_testBench_types.all; +use testBench_slv2string_FD7FE0FDE5409B5E.all; + +entity testBench is + port(result : out boolean); +end; + +architecture structural of testBench is + signal \c$ds_app_arg\ : Prop4_testBench_types.index_16; + signal \c$ds_app_arg_0\ : boolean; + signal s : Prop4_testBench_types.index_16 := to_unsigned(0,4); + -- prop4.hs:36:5-7 + signal \Prop4.testBench_clk\ : Prop4_testBench_types.clk_System; + signal z : Prop4_testBench_types.index_35; + signal result_1 : Prop4_testBench_types.index_18; + signal \c$ds_app_arg_1\ : boolean; + signal \c$result_rec\ : boolean; + signal s_0 : Prop4_testBench_types.index_18 := to_unsigned(0,5); + signal f2 : boolean; + signal \f'\ : boolean := false; + -- prop4.hs:10:1-45 + signal \c$ds_app_arg_2\ : Prop4_testBench_types.array_of_signed_2(0 to 0) := Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + signal result_2 : boolean; + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_3 : Prop4_testBench_types.Tup2; + -- prop4.hs:12:1-124 + signal \c$ds_app_arg_3\ : Prop4_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_4 : Prop4_testBench_types.Tup10; + signal result_5 : Prop4_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop4_testBench_types.Tup10; + -- prop4.hs:8:1-63 + signal \c$ds_app_arg_4\ : Prop4_testBench_types.array_of_signed_2(0 to 6) := Prop4_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_6 : boolean; + signal \c$app_arg_1\ : Prop4_testBench_types.array_of_signed_2(0 to 6); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_7 : Prop4_testBench_types.Tup2_1; + -- prop4.hs:16:1-125 + signal \c$ds_app_arg_5\ : Prop4_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) +, Tup10_sel1_unsigned_1 => to_unsigned(6,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(6,5) +, Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + signal result_8 : Prop4_testBench_types.Tup10; + signal result_9 : Prop4_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop4_testBench_types.Tup10; + -- prop4.hs:8:1-63 + signal \c$ds_app_arg_6\ : Prop4_testBench_types.array_of_signed_2(0 to 6) := Prop4_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_10 : boolean; + signal \c$app_arg_3\ : Prop4_testBench_types.array_of_signed_2(0 to 6); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_11 : Prop4_testBench_types.Tup2_1; + -- prop4.hs:14:1-125 + signal \c$ds_app_arg_7\ : Prop4_testBench_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_12 : Prop4_testBench_types.Tup10; + signal result_13 : Prop4_testBench_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop4_testBench_types.Tup10; + signal \c$ds_app_arg_8\ : Prop4_testBench_types.index_17; + signal \c$ds_app_arg_9\ : boolean; + signal s_1 : Prop4_testBench_types.index_17 := to_unsigned(0,5); + -- prop4.hs:29:1-9 + signal \c$Prop4.testBench_app_arg\ : Prop4_testBench_types.rst_System; + signal \c$ds_app_arg_selection_res\ : boolean; + signal \c$vec\ : Prop4_testBench_types.array_of_boolean(0 to 15); + signal result_selection_res : boolean; + signal \c$vec_0\ : Prop4_testBench_types.array_of_boolean(0 to 17); + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec_1\ : Prop4_testBench_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop4_testBench_types.Tup2_2; + signal \c$vec_2\ : Prop4_testBench_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop4_testBench_types.Tup2_2; + signal ds4_selection_res : boolean; + signal \c$vec_3\ : Prop4_testBench_types.array_of_signed_2(0 to 7); + signal \c$app_arg_1_1\ : Prop4_testBench_types.Tup2_3; + signal \c$vec_4\ : Prop4_testBench_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_0 : boolean; + signal \c$vec_5\ : Prop4_testBench_types.array_of_signed_2(0 to 7); + signal \c$app_arg_3_3\ : Prop4_testBench_types.Tup2_3; + signal \c$vec_6\ : Prop4_testBench_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_1 : boolean; + signal \c$ds_app_arg_selection_res_0\ : boolean; + signal \c$vec_7\ : Prop4_testBench_types.array_of_boolean(0 to 16); + +begin + \c$ds_app_arg_selection_res\ <= s < to_unsigned(15,4); + + \c$ds_app_arg\ <= s + to_unsigned(1,4) when \c$ds_app_arg_selection_res\ else + s; + + \c$vec\ <= Prop4_testBench_types.array_of_boolean'( false + , false + , false + , true + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false + , false ); + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 16-1; + begin + vec_index <= to_integer((signed(std_logic_vector(resize(s,64))))) + -- pragma translate_off + mod 16 + -- pragma translate_on + ; + \c$ds_app_arg_0\ <= \c$vec\(vec_index); + end block; + -- index end + + -- register begin + s_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + s <= to_unsigned(0,4); + elsif rising_edge(\Prop4.testBench_clk\) then + s <= \c$ds_app_arg\; + end if; + end process; + -- register end + + -- tbClockGen begin + -- pragma translate_off + clkGen : process is + constant half_periodH : time := 10000000 fs / 2; + constant half_periodL : time := 10000000 fs - half_periodH; + begin + \Prop4.testBench_clk\ <= '0'; + wait for 10000 ps; + while (not \c$result_rec\) loop + \Prop4.testBench_clk\ <= not \Prop4.testBench_clk\; + wait for half_periodH; + \Prop4.testBench_clk\ <= not \Prop4.testBench_clk\; + wait for half_periodL; + end loop; + wait; + end process; + -- pragma translate_on + -- tbClockGen end + + z <= resize(s_0,6) + resize(to_unsigned(1,5),6); + + result_selection_res <= z > to_unsigned(17,6); + + result_1 <= to_unsigned(17,5) when result_selection_res else + resize(z,5); + + \c$vec_0\ <= Prop4_testBench_types.array_of_boolean'( false + , false + , false + , false + , false + , false + , false + , false + , true + , true + , true + , true + , true + , true + , true + , false + , false + , false ); + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 18-1; + begin + vec_index_0 <= to_integer((signed(std_logic_vector(resize(s_0,64))))) + -- pragma translate_off + mod 18 + -- pragma translate_on + ; + \c$ds_app_arg_1\ <= \c$vec_0\(vec_index_0); + end block; + -- index end + + \c$result_rec\ <= \f'\ when \f'\ else + f2; + + -- register begin + s_0_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + s_0 <= to_unsigned(0,5); + elsif rising_edge(\Prop4.testBench_clk\) then + s_0 <= result_1; + end if; + end process; + -- register end + + -- assert begin + r_assert : block + -- pragma translate_off + signal actual : boolean; + signal expected : boolean; + -- pragma translate_on + begin + -- pragma translate_off + actual <= result_2; + expected <= \c$ds_app_arg_1\; + process(\Prop4.testBench_clk\) is + begin + if (rising_edge(\Prop4.testBench_clk\)) then + assert (toSLV(actual) = toSLV(expected)) report (("outputVerifier") & ", expected: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(expected)) & ", actual: " & testBench_slv2string_FD7FE0FDE5409B5E.slv2string(toSLV(actual))) severity error; + end if; + end process; + -- pragma translate_on + f2 <= \f'\; + end block; + -- assert end + + -- register begin + f_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \f'\ <= false; + elsif rising_edge(\Prop4.testBench_clk\) then + \f'\ <= (s_0 = to_unsigned(17,5)); + end if; + end process; + -- register end + + -- register begin + cds_app_arg_2_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_2\ <= Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_2\ <= result_3.Tup2_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec_1\ <= (Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec_1\(0 to 1-1),\c$vec_1\(1 to \c$vec_1\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_2_sel0_array_of_signed_2_0(0); + + fm1 <= result_4.Tup10_sel8_unsigned_8; + + fm2 <= result_4.Tup10_sel9_unsigned_9; + + \c$vec_2\ <= (Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_testBench_types.array_of_signed_2'(\c$ds_app_arg_2\))); + + \c$app_arg_7\ <= (\c$vec_2\(0 to 1-1),\c$vec_2\(1 to \c$vec_2\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_2_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_4.Tup10_sel6_unsigned_6; + + tm2 <= result_4.Tup10_sel7_unsigned_7; + + mm1 <= result_4.Tup10_sel4_unsigned_4; + + mm2 <= result_4.Tup10_sel5_unsigned_5; + + ff1 <= result_4.Tup10_sel2_unsigned_2; + + ff2 <= result_4.Tup10_sel3_unsigned_3; + + tt1 <= result_4.Tup10_sel0_unsigned_0; + + tt2 <= result_4.Tup10_sel1_unsigned_1; + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 1-1; + begin + vec_index_1 <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg_2\(vec_index_1); + end block; + -- index end + + result_3 <= ( Tup2_sel0_array_of_signed_2 => Prop4_testBench_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_3_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_3\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_3\ <= result_5.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_0_sel1_Tup10; + + result_5 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_3\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_3\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_10 or result_6)) or ((opcode = to_unsigned(1,1)) and result_10); + + ds4 <= \c$ds_app_arg_3\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_3\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_4_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_4\ <= Prop4_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_4\ <= result_7.Tup2_1_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_1_sel1_boolean; + + \c$vec_3\ <= (Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_testBench_types.array_of_signed_2'(\c$ds_app_arg_4\))); + + \c$app_arg_1_1\ <= (\c$vec_3\(0 to 7-1),\c$vec_3\(7 to \c$vec_3\'high)); + + \c$vec_4\ <= \c$app_arg_1_1\.Tup2_3_sel0_array_of_signed_2_0; + + -- imap begin + imap : block + function max (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_0 : for i in \c$app_arg_1\'range generate + begin + fun_1 : block + signal \c$app_arg_8\ : signed(63 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_9\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + begin + \c$app_arg_1\(i) <= \c$case_alt_7\; + + \c$app_arg_8\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_4\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tt2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tt1_1); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_5\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= ff2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= ff1_1); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_9\; + + \c$case_alt_selection_res_6\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= mm2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= mm1_1); + + \c$case_alt_9\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_7\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tm1_1) and \c$app_arg_9\); + + \c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_8\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= fm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= fm1_1) and \c$app_arg_9\); + + \c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$vec_4\(i); + + fm1_1 <= result_8.Tup10_sel8_unsigned_8; + + fm2_1 <= result_8.Tup10_sel9_unsigned_9; + + \c$app_arg_9\ <= \c$vec_4\(i) = to_signed(0,2); + + tm1_1 <= result_8.Tup10_sel6_unsigned_6; + + tm2_1 <= result_8.Tup10_sel7_unsigned_7; + + mm1_1 <= result_8.Tup10_sel4_unsigned_4; + + mm2_1 <= result_8.Tup10_sel5_unsigned_5; + + ff1_1 <= result_8.Tup10_sel2_unsigned_2; + + ff2_1 <= result_8.Tup10_sel3_unsigned_3; + + tt1_1 <= result_8.Tup10_sel0_unsigned_0; + + tt2_1 <= result_8.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_2 : block + signal vec_index_2 : integer range 0 to 7-1; + begin + vec_index_2 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_4\(vec_index_2); + end block; + -- index end + + result_7 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_1\ + , Tup2_1_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_5_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_5\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) + , Tup10_sel1_unsigned_1 => to_unsigned(6,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(6,5) + , Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_5\ <= result_9.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_0_sel1_Tup10; + + result_9 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_5\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_5\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (\c$ds_app_arg_9\ or \c$ds_app_arg_9\)) or ((opcode_0 = to_unsigned(1,1)) and \c$ds_app_arg_9\); + + ds4_0 <= \c$ds_app_arg_5\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_5\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_6_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_6\ <= Prop4_testBench_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_6\ <= result_11.Tup2_1_sel0_array_of_signed_2; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_1_sel1_boolean; + + \c$vec_5\ <= (Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(Prop4_testBench_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_testBench_types.array_of_signed_2'(\c$ds_app_arg_6\))); + + \c$app_arg_3_3\ <= (\c$vec_5\(0 to 7-1),\c$vec_5\(7 to \c$vec_5\'high)); + + \c$vec_6\ <= \c$app_arg_3_3\.Tup2_3_sel0_array_of_signed_2_0; + + -- imap begin + imap_1 : block + function max_0 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_2 : for i_0 in \c$app_arg_3\'range generate + begin + fun_2 : block + signal \c$app_arg_10\ : signed(63 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_11\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + begin + \c$app_arg_3\(i_0) <= \c$case_alt_12\; + + \c$app_arg_10\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tt2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tt1_2); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= ff2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= ff1_2); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_14\; + + \c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= mm2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= mm1_2); + + \c$case_alt_14\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tm1_2) and \c$app_arg_11\); + + \c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= fm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= fm1_2) and \c$app_arg_11\); + + \c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$vec_6\(i_0); + + fm1_2 <= result_12.Tup10_sel8_unsigned_8; + + fm2_2 <= result_12.Tup10_sel9_unsigned_9; + + \c$app_arg_11\ <= \c$vec_6\(i_0) = to_signed(0,2); + + tm1_2 <= result_12.Tup10_sel6_unsigned_6; + + tm2_2 <= result_12.Tup10_sel7_unsigned_7; + + mm1_2 <= result_12.Tup10_sel4_unsigned_4; + + mm2_2 <= result_12.Tup10_sel5_unsigned_5; + + ff1_2 <= result_12.Tup10_sel2_unsigned_2; + + ff2_2 <= result_12.Tup10_sel3_unsigned_3; + + tt1_2 <= result_12.Tup10_sel0_unsigned_0; + + tt2_2 <= result_12.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_3 : block + signal vec_index_3 : integer range 0 to 7-1; + begin + vec_index_3 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_6\(vec_index_3); + end block; + -- index end + + result_11 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_3\ + , Tup2_1_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_7_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + \c$ds_app_arg_7\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(\Prop4.testBench_clk\) then + \c$ds_app_arg_7\ <= result_13.Tup2_0_sel0_Tup3; + end if; + end process; + -- register end + + result_12 <= result_13.Tup2_0_sel1_Tup10; + + result_13 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_7\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_7\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (\c$ds_app_arg_0\ or \c$ds_app_arg_0\)) or ((opcode_1 = to_unsigned(1,1)) and \c$ds_app_arg_0\); + + ds4_1 <= \c$ds_app_arg_7\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_7\.Tup3_sel2_Tup10_1; + + \c$ds_app_arg_selection_res_0\ <= s_1 < to_unsigned(16,5); + + \c$ds_app_arg_8\ <= s_1 + to_unsigned(1,5) when \c$ds_app_arg_selection_res_0\ else + s_1; + + \c$vec_7\ <= Prop4_testBench_types.array_of_boolean'( false + , false + , false + , false + , false + , false + , false + , true + , true + , true + , true + , true + , true + , true + , false + , false + , false ); + + -- index begin + indexVec_4 : block + signal vec_index_4 : integer range 0 to 17-1; + begin + vec_index_4 <= to_integer((signed(std_logic_vector(resize(s_1,64))))) + -- pragma translate_off + mod 17 + -- pragma translate_on + ; + \c$ds_app_arg_9\ <= \c$vec_7\(vec_index_4); + end block; + -- index end + + -- register begin + s_1_register : process(\Prop4.testBench_clk\,\c$Prop4.testBench_app_arg\) + begin + if \c$Prop4.testBench_app_arg\ = '1' then + s_1 <= to_unsigned(0,5); + elsif rising_edge(\Prop4.testBench_clk\) then + s_1 <= \c$ds_app_arg_8\; + end if; + end process; + -- register end + + -- resetGen begin + resetGen : block + constant reset_delay : time := 10000 ps - 1 ps + (integer'(1) * 10000 ps); + begin + -- pragma translate_off + \c$Prop4.testBench_app_arg\ + <= '1', + '0' after reset_delay; + -- pragma translate_on + end block; + -- resetGen end + + result <= \c$result_rec\; + + +end; + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl new file mode 100644 index 0000000..dcabb4a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.testBench/testBench_slv2string_FD7FE0FDE5409B5E.vhdl @@ -0,0 +1,24 @@ +-- helper function of Clash.Explicit.Testbench.assert +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +package testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING; +end; + +package body testBench_slv2string_FD7FE0FDE5409B5E is + function slv2string (slv : std_logic_vector) return STRING is + variable result : string (1 to slv'length); + variable res_l : string (1 to 3); + variable r : integer; + begin + r := 1; + for i in slv'range loop + res_l := std_logic'image(slv(i)); + result(r) := res_l(2); + r := r + 1; + end loop; + return result; + end slv2string; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/Prop4_topEntity_types.vhdl b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/Prop4_topEntity_types.vhdl new file mode 100644 index 0000000..29a0fd9 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/Prop4_topEntity_types.vhdl @@ -0,0 +1,235 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package Prop4_topEntity_types is + + + type Tup2_2 is record + Tup2_2_sel0_boolean_0 : boolean; + Tup2_2_sel1_boolean_1 : boolean; + end record; + subtype rst_System is std_logic; + subtype en_System is boolean; + type Tup10 is record + Tup10_sel0_unsigned_0 : unsigned(4 downto 0); + Tup10_sel1_unsigned_1 : unsigned(4 downto 0); + Tup10_sel2_unsigned_2 : unsigned(4 downto 0); + Tup10_sel3_unsigned_3 : unsigned(4 downto 0); + Tup10_sel4_unsigned_4 : unsigned(4 downto 0); + Tup10_sel5_unsigned_5 : unsigned(4 downto 0); + Tup10_sel6_unsigned_6 : unsigned(4 downto 0); + Tup10_sel7_unsigned_7 : unsigned(4 downto 0); + Tup10_sel8_unsigned_8 : unsigned(4 downto 0); + Tup10_sel9_unsigned_9 : unsigned(4 downto 0); + end record; + type Tup3 is record + Tup3_sel0_unsigned : unsigned(0 downto 0); + Tup3_sel1_Tup10_0 : Tup10; + Tup3_sel2_Tup10_1 : Tup10; + end record; + subtype clk_System is std_logic; + + type Tup2_0 is record + Tup2_0_sel0_Tup3 : Tup3; + Tup2_0_sel1_Tup10 : Tup10; + end record; + type array_of_signed_2 is array (integer range <>) of signed(1 downto 0); + type Tup2_1 is record + Tup2_1_sel0_array_of_signed_2 : array_of_signed_2(0 to 6); + Tup2_1_sel1_boolean : boolean; + end record; + type Tup2_4 is record + Tup2_4_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 6); + Tup2_4_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + type Tup2 is record + Tup2_sel0_array_of_signed_2 : array_of_signed_2(0 to 0); + Tup2_sel1_boolean : boolean; + end record; + type Tup2_3 is record + Tup2_3_sel0_array_of_signed_2_0 : array_of_signed_2(0 to 0); + Tup2_3_sel1_array_of_signed_2_1 : array_of_signed_2(0 to 0); + end record; + function toSLV (b : in boolean) return std_logic_vector; + function fromSLV (sl : in std_logic_vector) return boolean; + function tagToEnum (s : in signed) return boolean; + function dataToTag (b : in boolean) return signed; + function toSLV (u : in unsigned) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return unsigned; + function toSLV (p : Tup2_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_2; + function toSLV (sl : in std_logic) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return std_logic; + function toSLV (p : Tup10) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup10; + function toSLV (p : Tup3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup3; + function toSLV (s : in signed) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return signed; + function toSLV (p : Tup2_0) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_0; + function toSLV (value : array_of_signed_2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2; + function toSLV (p : Tup2_1) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_1; + function toSLV (p : Tup2_4) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_4; + function toSLV (p : Tup2) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2; + function toSLV (p : Tup2_3) return std_logic_vector; + function fromSLV (slv : in std_logic_vector) return Tup2_3; +end; + +package body Prop4_topEntity_types is + function toSLV (b : in boolean) return std_logic_vector is + begin + if b then + return "1"; + else + return "0"; + end if; + end; + function fromSLV (sl : in std_logic_vector) return boolean is + begin + if sl = "1" then + return true; + else + return false; + end if; + end; + function tagToEnum (s : in signed) return boolean is + begin + if s = to_signed(0,64) then + return false; + else + return true; + end if; + end; + function dataToTag (b : in boolean) return signed is + begin + if b then + return to_signed(1,64); + else + return to_signed(0,64); + end if; + end; + function toSLV (u : in unsigned) return std_logic_vector is + begin + return std_logic_vector(u); + end; + function fromSLV (slv : in std_logic_vector) return unsigned is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return unsigned(islv); + end; + function toSLV (p : Tup2_2) return std_logic_vector is + begin + return (toSLV(p.Tup2_2_sel0_boolean_0) & toSLV(p.Tup2_2_sel1_boolean_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 1))); + end; + function toSLV (sl : in std_logic) return std_logic_vector is + begin + return std_logic_vector'(0 => sl); + end; + function fromSLV (slv : in std_logic_vector) return std_logic is + alias islv : std_logic_vector (0 to slv'length - 1) is slv; + begin + return islv(0); + end; + function toSLV (p : Tup10) return std_logic_vector is + begin + return (toSLV(p.Tup10_sel0_unsigned_0) & toSLV(p.Tup10_sel1_unsigned_1) & toSLV(p.Tup10_sel2_unsigned_2) & toSLV(p.Tup10_sel3_unsigned_3) & toSLV(p.Tup10_sel4_unsigned_4) & toSLV(p.Tup10_sel5_unsigned_5) & toSLV(p.Tup10_sel6_unsigned_6) & toSLV(p.Tup10_sel7_unsigned_7) & toSLV(p.Tup10_sel8_unsigned_8) & toSLV(p.Tup10_sel9_unsigned_9)); + end; + function fromSLV (slv : in std_logic_vector) return Tup10 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 4)),fromSLV(islv(5 to 9)),fromSLV(islv(10 to 14)),fromSLV(islv(15 to 19)),fromSLV(islv(20 to 24)),fromSLV(islv(25 to 29)),fromSLV(islv(30 to 34)),fromSLV(islv(35 to 39)),fromSLV(islv(40 to 44)),fromSLV(islv(45 to 49))); + end; + function toSLV (p : Tup3) return std_logic_vector is + begin + return (toSLV(p.Tup3_sel0_unsigned) & toSLV(p.Tup3_sel1_Tup10_0) & toSLV(p.Tup3_sel2_Tup10_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 0)),fromSLV(islv(1 to 50)),fromSLV(islv(51 to 100))); + end; + function toSLV (s : in signed) return std_logic_vector is + begin + return std_logic_vector(s); + end; + function fromSLV (slv : in std_logic_vector) return signed is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return signed(islv); + end; + function toSLV (p : Tup2_0) return std_logic_vector is + begin + return (toSLV(p.Tup2_0_sel0_Tup3) & toSLV(p.Tup2_0_sel1_Tup10)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_0 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 100)),fromSLV(islv(101 to 150))); + end; + function toSLV (value : array_of_signed_2) return std_logic_vector is + alias ivalue : array_of_signed_2(1 to value'length) is value; + variable result : std_logic_vector(1 to value'length * 2); + begin + for i in ivalue'range loop + result(((i - 1) * 2) + 1 to i*2) := toSLV(ivalue(i)); + end loop; + return result; + end; + function fromSLV (slv : in std_logic_vector) return array_of_signed_2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + variable result : array_of_signed_2(0 to slv'length / 2 - 1); + begin + for i in result'range loop + result(i) := fromSLV(islv(i * 2 to (i+1) * 2 - 1)); + end loop; + return result; + end; + function toSLV (p : Tup2_1) return std_logic_vector is + begin + return (toSLV(p.Tup2_1_sel0_array_of_signed_2) & toSLV(p.Tup2_1_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_1 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 14))); + end; + function toSLV (p : Tup2_4) return std_logic_vector is + begin + return (toSLV(p.Tup2_4_sel0_array_of_signed_2_0) & toSLV(p.Tup2_4_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_4 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 13)),fromSLV(islv(14 to 15))); + end; + function toSLV (p : Tup2) return std_logic_vector is + begin + return (toSLV(p.Tup2_sel0_array_of_signed_2) & toSLV(p.Tup2_sel1_boolean)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 2))); + end; + function toSLV (p : Tup2_3) return std_logic_vector is + begin + return (toSLV(p.Tup2_3_sel0_array_of_signed_2_0) & toSLV(p.Tup2_3_sel1_array_of_signed_2_1)); + end; + function fromSLV (slv : in std_logic_vector) return Tup2_3 is + alias islv : std_logic_vector(0 to slv'length - 1) is slv; + begin + return (fromSLV(islv(0 to 1)),fromSLV(islv(2 to 3))); + end; +end; + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/clash-manifest.json b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/clash-manifest.json new file mode 100644 index 0000000..9816ce9 --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/clash-manifest.json @@ -0,0 +1,101 @@ +{ + "components": [ + "topEntity" + ], + "flags": [ + 20, + 20 + ], + "hash": "263b88e196839de8822f39fa71c05d7d781aa002e0e37046b003102dfdad08eb", + "dependencies": { + "transitive": [] + }, + "version": "unstable", + "files": [ + { + "name": "topEntity.sdc", + "sha256": "13d4c1aafcc09a84d81d3b60d513cb901384a10e27e5a5a16572a600f15895f3" + }, + { + "name": "Prop4_topEntity_types.vhdl", + "sha256": "af20d79bba56606cc5d286e865c0941c07c1a0a673eb4aa8e622058591aa4f44" + }, + { + "name": "topEntity.vhdl", + "sha256": "0b5001176be1972eaa22a7a4952a196c35dbd63ea978e03f923aaedd6d4ddf99" + } + ], + "top_component": { + "ports_flat": [ + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "clk", + "is_clock": true, + "type_name": "clk.Prop4_topEntity_types.clk_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "rst", + "is_clock": false, + "type_name": "rst.Prop4_topEntity_types.rst_System" + }, + { + "direction": "in", + "domain": "System", + "width": 1, + "name": "en", + "is_clock": false, + "type_name": "en.Prop4_topEntity_types.en_System" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_0", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "in", + "width": 1, + "name": "eta1_1", + "is_clock": false, + "type_name": "boolean" + }, + { + "direction": "out", + "width": 1, + "name": "result", + "is_clock": false, + "type_name": "boolean" + } + ], + "name": "topEntity" + }, + "domains": { + "System": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "XilinxSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Synchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + }, + "IntelSystem": { + "period": 10000, + "init_behavior": "Defined", + "reset_kind": "Asynchronous", + "active_edge": "Rising", + "reset_polarity": "ActiveHigh" + } + } +} \ No newline at end of file diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.sdc b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.sdc new file mode 100644 index 0000000..885f86a --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.sdc @@ -0,0 +1,2 @@ +create_clock -name {clk} -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] + diff --git a/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.vhdl b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.vhdl new file mode 100644 index 0000000..17c7cfb --- /dev/null +++ b/tests/washing_machine/properties/vhdl_prop4/Prop4.topEntity/topEntity.vhdl @@ -0,0 +1,733 @@ +-- Automatically generated VHDL-93 +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.MATH_REAL.ALL; +use std.textio.all; +use work.all; +use work.Prop4_topEntity_types.all; + +entity topEntity is + port(-- clock + clk : in Prop4_topEntity_types.clk_System; + -- reset + rst : in Prop4_topEntity_types.rst_System; + -- enable + en : in Prop4_topEntity_types.en_System; + eta1_0 : in boolean; + eta1_1 : in boolean; + result : out boolean); +end; + +architecture structural of topEntity is + -- prop4.hs:18:1-212 + signal inp1 : boolean; + -- prop4.hs:18:1-212 + signal inp2 : boolean; + -- prop4.hs:10:1-45 + signal \c$ds_app_arg\ : Prop4_topEntity_types.array_of_signed_2(0 to 0) := Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + signal \c$case_alt\ : signed(1 downto 0); + signal \c$case_alt_0\ : signed(1 downto 0); + signal \c$case_alt_1\ : signed(1 downto 0); + signal \c$case_alt_2\ : signed(1 downto 0); + signal \c$case_alt_3\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2 : unsigned(4 downto 0); + signal \c$app_arg\ : boolean; + -- Queue.hs:20:1-12 + signal tm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2 : unsigned(4 downto 0); + signal \c$app_arg_0\ : signed(1 downto 0); + signal result_1 : Prop4_topEntity_types.Tup2; + -- prop4.hs:12:1-124 + signal \c$ds_app_arg_0\ : Prop4_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(0,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_2 : Prop4_topEntity_types.Tup10; + signal result_3 : Prop4_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4 : Prop4_topEntity_types.Tup10; + -- prop4.hs:8:1-63 + signal \c$ds_app_arg_1\ : Prop4_topEntity_types.array_of_signed_2(0 to 6) := Prop4_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_4 : boolean; + signal \c$app_arg_1\ : Prop4_topEntity_types.array_of_signed_2(0 to 6); + signal \c$app_arg_2\ : signed(1 downto 0); + signal result_5 : Prop4_topEntity_types.Tup2_1; + -- prop4.hs:16:1-125 + signal \c$ds_app_arg_2\ : Prop4_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) +, Tup10_sel1_unsigned_1 => to_unsigned(6,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(0,5) +, Tup10_sel5_unsigned_5 => to_unsigned(0,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(6,5) +, Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + signal result_6 : Prop4_topEntity_types.Tup10; + signal result_7 : Prop4_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_0 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_0 : Prop4_topEntity_types.Tup10; + -- prop4.hs:8:1-63 + signal \c$ds_app_arg_3\ : Prop4_topEntity_types.array_of_signed_2(0 to 6) := Prop4_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + signal result_8 : boolean; + signal \c$app_arg_3\ : Prop4_topEntity_types.array_of_signed_2(0 to 6); + signal \c$app_arg_4\ : signed(1 downto 0); + signal result_9 : Prop4_topEntity_types.Tup2_1; + -- prop4.hs:14:1-125 + signal \c$ds_app_arg_4\ : Prop4_topEntity_types.Tup3 := ( Tup3_sel0_unsigned => to_unsigned(1,1) +, Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) +, Tup10_sel1_unsigned_1 => to_unsigned(31,5) +, Tup10_sel2_unsigned_2 => to_unsigned(0,5) +, Tup10_sel3_unsigned_3 => to_unsigned(0,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) +, Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) +, Tup10_sel1_unsigned_1 => to_unsigned(0,5) +, Tup10_sel2_unsigned_2 => to_unsigned(31,5) +, Tup10_sel3_unsigned_3 => to_unsigned(31,5) +, Tup10_sel4_unsigned_4 => to_unsigned(31,5) +, Tup10_sel5_unsigned_5 => to_unsigned(31,5) +, Tup10_sel6_unsigned_6 => to_unsigned(31,5) +, Tup10_sel7_unsigned_7 => to_unsigned(31,5) +, Tup10_sel8_unsigned_8 => to_unsigned(31,5) +, Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + signal result_10 : Prop4_topEntity_types.Tup10; + signal result_11 : Prop4_topEntity_types.Tup2_0; + -- ProcessingElement.hs:9:1-777 + signal opcode_1 : unsigned(0 downto 0); + -- ProcessingElement.hs:9:1-777 + signal ds4_1 : Prop4_topEntity_types.Tup10; + signal eta1 : Prop4_topEntity_types.Tup2_2; + signal \c$case_alt_selection_res\ : boolean; + signal \c$case_alt_selection_res_0\ : boolean; + signal \c$case_alt_selection_res_1\ : boolean; + signal \c$case_alt_selection_res_2\ : boolean; + signal \c$case_alt_selection_res_3\ : boolean; + signal \c$vec\ : Prop4_topEntity_types.array_of_signed_2(0 to 1); + signal \c$case_alt_sel_alt_9\ : Prop4_topEntity_types.Tup2_3; + signal \c$vec_0\ : Prop4_topEntity_types.array_of_signed_2(0 to 1); + signal \c$app_arg_7\ : Prop4_topEntity_types.Tup2_3; + signal ds4_selection_res : boolean; + signal \c$vec_1\ : Prop4_topEntity_types.array_of_signed_2(0 to 7); + signal \c$app_arg_1_1\ : Prop4_topEntity_types.Tup2_4; + signal \c$vec_2\ : Prop4_topEntity_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_0 : boolean; + signal \c$vec_3\ : Prop4_topEntity_types.array_of_signed_2(0 to 7); + signal \c$app_arg_3_3\ : Prop4_topEntity_types.Tup2_4; + signal \c$vec_4\ : Prop4_topEntity_types.array_of_signed_2(0 to 6); + signal ds4_selection_res_1 : boolean; + +begin + eta1 <= ( Tup2_2_sel0_boolean_0 => eta1_0 + , Tup2_2_sel1_boolean_1 => eta1_1 ); + + inp1 <= eta1.Tup2_2_sel0_boolean_0; + + inp2 <= eta1.Tup2_2_sel1_boolean_1; + + -- register begin + cds_app_arg_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg\ <= Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2)); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg\ <= result_1.Tup2_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result <= result_1.Tup2_sel1_boolean; + + \c$case_alt_selection_res\ <= (to_unsigned(0,5) <= tt2) and (to_unsigned(0,5) >= tt1); + + \c$case_alt\ <= to_signed(1,2) when \c$case_alt_selection_res\ else + \c$case_alt_0\; + + \c$case_alt_selection_res_0\ <= (to_unsigned(0,5) <= ff2) and (to_unsigned(0,5) >= ff1); + + \c$case_alt_0\ <= to_signed(-1,2) when \c$case_alt_selection_res_0\ else + \c$case_alt_1\; + + \c$case_alt_selection_res_1\ <= (to_unsigned(0,5) <= mm2) and (to_unsigned(0,5) >= mm1); + + \c$case_alt_1\ <= to_signed(0,2) when \c$case_alt_selection_res_1\ else + \c$case_alt_2\; + + \c$case_alt_selection_res_2\ <= (to_unsigned(0,5) <= tm2) and ((to_unsigned(0,5) >= tm1) and \c$app_arg\); + + \c$case_alt_2\ <= to_signed(1,2) when \c$case_alt_selection_res_2\ else + \c$case_alt_3\; + + \c$case_alt_selection_res_3\ <= (to_unsigned(0,5) <= fm2) and ((to_unsigned(0,5) >= fm1) and \c$app_arg\); + + \c$vec\ <= (Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$case_alt_sel_alt_9\ <= (\c$vec\(0 to 1-1),\c$vec\(1 to \c$vec\'high)); + + \c$case_alt_3\ <= to_signed(-1,2) when \c$case_alt_selection_res_3\ else + \c$case_alt_sel_alt_9\.Tup2_3_sel0_array_of_signed_2_0(0); + + fm1 <= result_2.Tup10_sel8_unsigned_8; + + fm2 <= result_2.Tup10_sel9_unsigned_9; + + \c$vec_0\ <= (Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_topEntity_types.array_of_signed_2'(\c$ds_app_arg\))); + + \c$app_arg_7\ <= (\c$vec_0\(0 to 1-1),\c$vec_0\(1 to \c$vec_0\'high)); + + \c$app_arg\ <= \c$app_arg_7\.Tup2_3_sel0_array_of_signed_2_0(0) = to_signed(0,2); + + tm1 <= result_2.Tup10_sel6_unsigned_6; + + tm2 <= result_2.Tup10_sel7_unsigned_7; + + mm1 <= result_2.Tup10_sel4_unsigned_4; + + mm2 <= result_2.Tup10_sel5_unsigned_5; + + ff1 <= result_2.Tup10_sel2_unsigned_2; + + ff2 <= result_2.Tup10_sel3_unsigned_3; + + tt1 <= result_2.Tup10_sel0_unsigned_0; + + tt2 <= result_2.Tup10_sel1_unsigned_1; + + -- index begin + indexVec : block + signal vec_index : integer range 0 to 1-1; + begin + vec_index <= to_integer(to_signed(0,64)) + -- pragma translate_off + mod 1 + -- pragma translate_on + ; + \c$app_arg_0\ <= \c$ds_app_arg\(vec_index); + end block; + -- index end + + result_1 <= ( Tup2_sel0_array_of_signed_2 => Prop4_topEntity_types.array_of_signed_2'(0 => \c$case_alt\) + , Tup2_sel1_boolean => \c$app_arg_0\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_0_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_0\ <= ( Tup3_sel0_unsigned => to_unsigned(0,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_0\ <= result_3.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_2 <= result_3.Tup2_0_sel1_Tup10; + + result_3 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_0\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4.Tup10_sel9_unsigned_9 ) ); + + opcode <= \c$ds_app_arg_0\.Tup3_sel0_unsigned; + + ds4_selection_res <= ((opcode = to_unsigned(0,1)) and (result_8 or result_4)) or ((opcode = to_unsigned(1,1)) and result_8); + + ds4 <= \c$ds_app_arg_0\.Tup3_sel1_Tup10_0 when ds4_selection_res else + \c$ds_app_arg_0\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_1_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_1\ <= Prop4_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_1\ <= result_5.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_4 <= result_5.Tup2_1_sel1_boolean; + + \c$vec_1\ <= (Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_topEntity_types.array_of_signed_2'(\c$ds_app_arg_1\))); + + \c$app_arg_1_1\ <= (\c$vec_1\(0 to 7-1),\c$vec_1\(7 to \c$vec_1\'high)); + + \c$vec_2\ <= \c$app_arg_1_1\.Tup2_4_sel0_array_of_signed_2_0; + + -- imap begin + imap : block + function max (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_0 : for i in \c$app_arg_1\'range generate + begin + fun_1 : block + signal \c$app_arg_8\ : signed(63 downto 0); + signal \c$case_alt_7\ : signed(1 downto 0); + signal \c$case_alt_8\ : signed(1 downto 0); + signal \c$case_alt_9\ : signed(1 downto 0); + signal \c$case_alt_10\ : signed(1 downto 0); + signal \c$case_alt_11\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_1 : unsigned(4 downto 0); + signal \c$app_arg_9\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_1 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_1 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_4\ : boolean; + signal \c$case_alt_selection_res_5\ : boolean; + signal \c$case_alt_selection_res_6\ : boolean; + signal \c$case_alt_selection_res_7\ : boolean; + signal \c$case_alt_selection_res_8\ : boolean; + begin + \c$app_arg_1\(i) <= \c$case_alt_7\; + + \c$app_arg_8\ <= signed(std_logic_vector(resize(to_unsigned(i,max(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_4\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tt2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tt1_1); + + \c$case_alt_7\ <= to_signed(1,2) when \c$case_alt_selection_res_4\ else + \c$case_alt_8\; + + \c$case_alt_selection_res_5\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= ff2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= ff1_1); + + \c$case_alt_8\ <= to_signed(-1,2) when \c$case_alt_selection_res_5\ else + \c$case_alt_9\; + + \c$case_alt_selection_res_6\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= mm2_1) and ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= mm1_1); + + \c$case_alt_9\ <= to_signed(0,2) when \c$case_alt_selection_res_6\ else + \c$case_alt_10\; + + \c$case_alt_selection_res_7\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= tm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= tm1_1) and \c$app_arg_9\); + + \c$case_alt_10\ <= to_signed(1,2) when \c$case_alt_selection_res_7\ else + \c$case_alt_11\; + + \c$case_alt_selection_res_8\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) <= fm2_1) and (((resize(unsigned(std_logic_vector(\c$app_arg_8\)),5)) >= fm1_1) and \c$app_arg_9\); + + \c$case_alt_11\ <= to_signed(-1,2) when \c$case_alt_selection_res_8\ else + \c$vec_2\(i); + + fm1_1 <= result_6.Tup10_sel8_unsigned_8; + + fm2_1 <= result_6.Tup10_sel9_unsigned_9; + + \c$app_arg_9\ <= \c$vec_2\(i) = to_signed(0,2); + + tm1_1 <= result_6.Tup10_sel6_unsigned_6; + + tm2_1 <= result_6.Tup10_sel7_unsigned_7; + + mm1_1 <= result_6.Tup10_sel4_unsigned_4; + + mm2_1 <= result_6.Tup10_sel5_unsigned_5; + + ff1_1 <= result_6.Tup10_sel2_unsigned_2; + + ff2_1 <= result_6.Tup10_sel3_unsigned_3; + + tt1_1 <= result_6.Tup10_sel0_unsigned_0; + + tt2_1 <= result_6.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_0 : block + signal vec_index_0 : integer range 0 to 7-1; + begin + vec_index_0 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_2\ <= \c$ds_app_arg_1\(vec_index_0); + end block; + -- index end + + result_5 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_1\ + , Tup2_1_sel1_boolean => \c$app_arg_2\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_2_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_2\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(4,5) + , Tup10_sel1_unsigned_1 => to_unsigned(6,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(0,5) + , Tup10_sel5_unsigned_5 => to_unsigned(0,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(6,5) + , Tup10_sel9_unsigned_9 => to_unsigned(6,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_2\ <= result_7.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_6 <= result_7.Tup2_0_sel1_Tup10; + + result_7 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_2\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_0.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_0.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_0.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_0.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_0.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_0.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_0.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_0.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_0.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_0.Tup10_sel9_unsigned_9 ) ); + + opcode_0 <= \c$ds_app_arg_2\.Tup3_sel0_unsigned; + + ds4_selection_res_0 <= ((opcode_0 = to_unsigned(0,1)) and (inp2 or inp2)) or ((opcode_0 = to_unsigned(1,1)) and inp2); + + ds4_0 <= \c$ds_app_arg_2\.Tup3_sel1_Tup10_0 when ds4_selection_res_0 else + \c$ds_app_arg_2\.Tup3_sel2_Tup10_1; + + -- register begin + cds_app_arg_3_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_3\ <= Prop4_topEntity_types.array_of_signed_2'( to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) + , to_signed(0,2) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_3\ <= result_9.Tup2_1_sel0_array_of_signed_2; + end if; + end if; + end process; + -- register end + + result_8 <= result_9.Tup2_1_sel1_boolean; + + \c$vec_3\ <= (Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(Prop4_topEntity_types.array_of_signed_2'(0 => to_signed(0,2))) & Prop4_topEntity_types.array_of_signed_2'(\c$ds_app_arg_3\))); + + \c$app_arg_3_3\ <= (\c$vec_3\(0 to 7-1),\c$vec_3\(7 to \c$vec_3\'high)); + + \c$vec_4\ <= \c$app_arg_3_3\.Tup2_4_sel0_array_of_signed_2_0; + + -- imap begin + imap_1 : block + function max_0 (l,r : in natural) return natural is + begin + if l > r then return l; + else return r; + end if; + end function; + begin + imap_2 : for i_0 in \c$app_arg_3\'range generate + begin + fun_2 : block + signal \c$app_arg_10\ : signed(63 downto 0); + signal \c$case_alt_12\ : signed(1 downto 0); + signal \c$case_alt_13\ : signed(1 downto 0); + signal \c$case_alt_14\ : signed(1 downto 0); + signal \c$case_alt_15\ : signed(1 downto 0); + signal \c$case_alt_16\ : signed(1 downto 0); + -- Queue.hs:20:1-12 + signal fm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal fm2_2 : unsigned(4 downto 0); + signal \c$app_arg_11\ : boolean; + -- Queue.hs:20:1-12 + signal tm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal mm2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal ff2_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt1_2 : unsigned(4 downto 0); + -- Queue.hs:20:1-12 + signal tt2_2 : unsigned(4 downto 0); + signal \c$case_alt_selection_res_9\ : boolean; + signal \c$case_alt_selection_res_10\ : boolean; + signal \c$case_alt_selection_res_11\ : boolean; + signal \c$case_alt_selection_res_12\ : boolean; + signal \c$case_alt_selection_res_13\ : boolean; + begin + \c$app_arg_3\(i_0) <= \c$case_alt_12\; + + \c$app_arg_10\ <= signed(std_logic_vector(resize(to_unsigned(i_0,max_0(1,integer(ceil(log2(real(7)))))),64))); + + \c$case_alt_selection_res_9\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tt2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tt1_2); + + \c$case_alt_12\ <= to_signed(1,2) when \c$case_alt_selection_res_9\ else + \c$case_alt_13\; + + \c$case_alt_selection_res_10\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= ff2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= ff1_2); + + \c$case_alt_13\ <= to_signed(-1,2) when \c$case_alt_selection_res_10\ else + \c$case_alt_14\; + + \c$case_alt_selection_res_11\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= mm2_2) and ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= mm1_2); + + \c$case_alt_14\ <= to_signed(0,2) when \c$case_alt_selection_res_11\ else + \c$case_alt_15\; + + \c$case_alt_selection_res_12\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= tm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= tm1_2) and \c$app_arg_11\); + + \c$case_alt_15\ <= to_signed(1,2) when \c$case_alt_selection_res_12\ else + \c$case_alt_16\; + + \c$case_alt_selection_res_13\ <= ((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) <= fm2_2) and (((resize(unsigned(std_logic_vector(\c$app_arg_10\)),5)) >= fm1_2) and \c$app_arg_11\); + + \c$case_alt_16\ <= to_signed(-1,2) when \c$case_alt_selection_res_13\ else + \c$vec_4\(i_0); + + fm1_2 <= result_10.Tup10_sel8_unsigned_8; + + fm2_2 <= result_10.Tup10_sel9_unsigned_9; + + \c$app_arg_11\ <= \c$vec_4\(i_0) = to_signed(0,2); + + tm1_2 <= result_10.Tup10_sel6_unsigned_6; + + tm2_2 <= result_10.Tup10_sel7_unsigned_7; + + mm1_2 <= result_10.Tup10_sel4_unsigned_4; + + mm2_2 <= result_10.Tup10_sel5_unsigned_5; + + ff1_2 <= result_10.Tup10_sel2_unsigned_2; + + ff2_2 <= result_10.Tup10_sel3_unsigned_3; + + tt1_2 <= result_10.Tup10_sel0_unsigned_0; + + tt2_2 <= result_10.Tup10_sel1_unsigned_1; + + + end block; + end generate; + end block; + -- imap end + + -- index begin + indexVec_1 : block + signal vec_index_1 : integer range 0 to 7-1; + begin + vec_index_1 <= to_integer(to_signed(6,64)) + -- pragma translate_off + mod 7 + -- pragma translate_on + ; + \c$app_arg_4\ <= \c$ds_app_arg_3\(vec_index_1); + end block; + -- index end + + result_9 <= ( Tup2_1_sel0_array_of_signed_2 => \c$app_arg_3\ + , Tup2_1_sel1_boolean => \c$app_arg_4\ = to_signed(1,2) ); + + -- register begin + cds_app_arg_4_register : process(clk,rst) + begin + if rst = '1' then + \c$ds_app_arg_4\ <= ( Tup3_sel0_unsigned => to_unsigned(1,1) + , Tup3_sel1_Tup10_0 => ( Tup10_sel0_unsigned_0 => to_unsigned(31,5) + , Tup10_sel1_unsigned_1 => to_unsigned(31,5) + , Tup10_sel2_unsigned_2 => to_unsigned(0,5) + , Tup10_sel3_unsigned_3 => to_unsigned(0,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) + , Tup3_sel2_Tup10_1 => ( Tup10_sel0_unsigned_0 => to_unsigned(0,5) + , Tup10_sel1_unsigned_1 => to_unsigned(0,5) + , Tup10_sel2_unsigned_2 => to_unsigned(31,5) + , Tup10_sel3_unsigned_3 => to_unsigned(31,5) + , Tup10_sel4_unsigned_4 => to_unsigned(31,5) + , Tup10_sel5_unsigned_5 => to_unsigned(31,5) + , Tup10_sel6_unsigned_6 => to_unsigned(31,5) + , Tup10_sel7_unsigned_7 => to_unsigned(31,5) + , Tup10_sel8_unsigned_8 => to_unsigned(31,5) + , Tup10_sel9_unsigned_9 => to_unsigned(31,5) ) ); + elsif rising_edge(clk) then + if en then + \c$ds_app_arg_4\ <= result_11.Tup2_0_sel0_Tup3; + end if; + end if; + end process; + -- register end + + result_10 <= result_11.Tup2_0_sel1_Tup10; + + result_11 <= ( Tup2_0_sel0_Tup3 => \c$ds_app_arg_4\ + , Tup2_0_sel1_Tup10 => ( Tup10_sel0_unsigned_0 => ds4_1.Tup10_sel0_unsigned_0 + , Tup10_sel1_unsigned_1 => ds4_1.Tup10_sel1_unsigned_1 + , Tup10_sel2_unsigned_2 => ds4_1.Tup10_sel2_unsigned_2 + , Tup10_sel3_unsigned_3 => ds4_1.Tup10_sel3_unsigned_3 + , Tup10_sel4_unsigned_4 => ds4_1.Tup10_sel4_unsigned_4 + , Tup10_sel5_unsigned_5 => ds4_1.Tup10_sel5_unsigned_5 + , Tup10_sel6_unsigned_6 => ds4_1.Tup10_sel6_unsigned_6 + , Tup10_sel7_unsigned_7 => ds4_1.Tup10_sel7_unsigned_7 + , Tup10_sel8_unsigned_8 => ds4_1.Tup10_sel8_unsigned_8 + , Tup10_sel9_unsigned_9 => ds4_1.Tup10_sel9_unsigned_9 ) ); + + opcode_1 <= \c$ds_app_arg_4\.Tup3_sel0_unsigned; + + ds4_selection_res_1 <= ((opcode_1 = to_unsigned(0,1)) and (inp1 or inp1)) or ((opcode_1 = to_unsigned(1,1)) and inp1); + + ds4_1 <= \c$ds_app_arg_4\.Tup3_sel1_Tup10_0 when ds4_selection_res_1 else + \c$ds_app_arg_4\.Tup3_sel2_Tup10_1; + + +end; + diff --git a/tests/washing_machine/simple_controller/washing_machine.ino b/tests/washing_machine/simple_controller/washing_machine.ino new file mode 100644 index 0000000..cfa1bc5 --- /dev/null +++ b/tests/washing_machine/simple_controller/washing_machine.ino @@ -0,0 +1,101 @@ +#define start 2; +#define fill 3; +#define soak 4; +#define spin_wash 5; +#define rinse 6; +#define drain 7; +#define spin_dry 8; +#define mode 9; + +int status; + +//start,fill,soak,dry +void setup() { + // put your setup code here, to run once: + Serial.begin(9600); + + digitalWrite(2,LOW); + digitalWrite(3,LOW); + digitalWrite(4,LOW); + digitalWrite(5,LOW); + digitalWrite(6,LOW); + digitalWrite(7,LOW); + digitalWrite(8,LOW); + +} + +void loop() { + // put your main code here, to run repeatedly: + + status = 2; + + switch(status){ +/*normal*/case 1: digitalWrite(2,HIGH); //start + delay(1000); + digitalWrite(2,LOW); //start + digitalWrite(3,HIGH); //fill + delay(4000); + digitalWrite(3,LOW); + digitalWrite(4,HIGH); //soak + delay(2000); + digitalWrite(4,LOW); + digitalWrite(5,HIGH); //wash + delay(5000); + digitalWrite(5,LOW); + digitalWrite(6,HIGH); //rinse + delay(3000); + digitalWrite(6,LOW); + digitalWrite(7,HIGH); //drain + delay(1000); + digitalWrite(7,LOW); + digitalWrite(8,HIGH); //dry + delay(4000); + digitalWrite(8,LOW); + break; +/*fast*/case 2: digitalWrite(2,HIGH); //start + delay(1000); + digitalWrite(3,HIGH); //fill + delay(2000); + digitalWrite(3,LOW); //fill + digitalWrite(2,LOW); //start -> stop + digitalWrite(4,HIGH); //soak + delay(4000); + digitalWrite(4,LOW); //soak + digitalWrite(5,HIGH); //wash + delay(4000); + digitalWrite(5,LOW); //wash + digitalWrite(6,HIGH); //rinse + delay(2000); + digitalWrite(6,LOW); //rinse + digitalWrite(7,HIGH); //drain + digitalWrite(8,HIGH); //dry + delay(4000); + digitalWrite(8,LOW); //dry + digitalWrite(7,LOW); //drain + break; +/*abnormal*/case 3: + digitalWrite(2,HIGH); //start + digitalWrite(3,HIGH); //fill + delay(4000); + digitalWrite(3,LOW); + digitalWrite(4,HIGH); //soak + delay(2000); + digitalWrite(4,LOW); + digitalWrite(5,HIGH); //wash + delay(5000); + digitalWrite(5,LOW); + digitalWrite(6,HIGH); //rinse + delay(3000); + digitalWrite(6,LOW); + digitalWrite(7,HIGH); //drain + delay(1000); + digitalWrite(7,LOW); + digitalWrite(8,HIGH); //dry + delay(4000); + digitalWrite(8,LOW); + break; + + } + + +}