34 lines
1.8 KiB
Plaintext
34 lines
1.8 KiB
Plaintext
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Registers involved:
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GPIO:
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DDRB: Data Direction Register for Port B= 0xFF for output
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PWM Module:
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OCR0A: Output Compare Register A=Value here is compared with the Timer value,and when the value matches, the specific pin[pin OC0A(pin 13) in this case] gets toggled
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TCCR0A: Timer/Counter 0 Control Register A = 0x83
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Bit [7:6]= COM0A-Compare Output Mode A = 10-Non-inverting PWM-Clear OC0A on Compare Match
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Bit [1:0]= WGM[1:0]- Waveform Generation Mode=11- for non-inverting fast PWM.
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TCCR0B: Timer/Counter 0 Control Register B = 0x03
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Bit [2:0] – CS0[2:0]-Clock Select = 011- for prescaler=64 in order to obtain frequency of 1kHz
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OCR2A: Output Compare Register A=Value here is compared with the Timer value,and when the value matches, the specific pin[pin OC2A(pin 10) in this case] gets toggled. The value given here is such that the duty cycle is 47 percent, a little less than 50 percent. This change in duty cycle is done in order to induce deadtime in the inverted signal.
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TCCR2A: Timer/Counter 2 Control Register A = 0xC3
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Bit [7:6]= COM0A-Compare Output Mode A = 11-Inverting PWM-Clear OC2A on Compare Match
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Bit [1:0]= WGM[1:0]- Waveform Generation Mode=11- for fast PWM.
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TCCR2B: Timer/Counter 2 Control Register B = 0x04
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Bit [2:0] – CS0[2:0]-Clock Select = 100- for prescaler=64 in order to obtain frequency of 1kHz
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The concept of Deadtime:
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One of the main problems in pulse width modulated voltage source inverter (PWM-VSI) drives is the nonlinear voltage
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gain caused by non-ideal characteristics of the power inverter.
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The most important nonlinearity is caused by the necessary
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blanking time between top and bottom switch to avoid inverter
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leg shoot-through of the DC bus circuit. The type of the switch
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and pre-driver characteristics determine amount of the
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necessary blank time.
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