2022-10-04 18:52:43 +05:30
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Registers involved:
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GPIO:
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DDRL: Data Direction Register for Port L= 0xFF for output
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DDRC: Data Direction Register for Port C= 0xFF for output
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ADC:
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ADCSRA: ADC Control and Status Register A = 0x87
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Bit 7= 1= ADC Enabled
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Bit 6= ADSC: ADC Start Conversion Bit- In Single Conversion mode, write this bit to one to start each conversion.
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Bit 4= ADIF: ADC Interrupt Flag- This bit is set when an ADC conversion completes and the Data Registers are updated
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Bit [2:0] = 111 = Prescaler-128
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ADMUX: ADC Multiplexer = 0xC0
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2022-10-05 20:05:08 +05:30
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Bit [7:6] = 01 = Vref= AVcc = 5V
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Bit 5 = 1 = Result(10-bits-wide) is left-justified
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2022-10-04 18:52:43 +05:30
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Bit [4:0] = 00000 = Input at ADC0
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ADCL: ADC Data Register Lower= stores the lower 8 bits of result of conversion
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ADCH: ADC Data Register Higher= stores the higher 8 bits of result of conversion
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