2022-10-04 18:52:43 +05:30
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Registers involved:
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GPIO:
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DDRA: Data Direction Register for Port A= 0xFF for output
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2022-10-05 20:05:08 +05:30
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DDRC: Data Direction Register for Port C= 0xFF for output
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2022-10-04 18:52:43 +05:30
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PORTD: Port D Data Register= set as 0xFF to activate pull up registers
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Input Capture Unit(ICU):
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TCCR1A: Timer/Counter 1 Control Register A = 0x00 for normal mode of opearation
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TCCR1B: Timer/Counter 1 Control Register B = 0x41
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Bit 7= ICNCn = ICU Noise Canceller= 0-Disabled
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Bit 6= ICU Capture Edge select bit: when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
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Bit [2:0] = 001 = Prescaler-1(i.e. no clock division)
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TIFR1: Timer/Counter1 Interrupt Flag Register
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Bit 5= ICF1= Timer/Counter Input Capture Flag 1
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This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the
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WGM1[3:0] to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
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ICR1L: Input Capture Register 1 Lower= stores the lower 8 bits of result
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ICR1H: Input Capture Register 1 Higher= stores the higher 8 bits of result
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