38 lines
1.9 KiB
Haskell
38 lines
1.9 KiB
Haskell
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module Prop4 where
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import Clash.Explicit.Testbench
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import Clash.Prelude
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import ProcessingElement(processingElement)
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import Queue(queue,queuetest)
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import Queue30(queue30,queuetest30)
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queue_mealy11 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>Nil) inp
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queue_mealy12 inp = mealy queue (0:>0:>0:>0:>0:>0:>0:>Nil) inp
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queue_mealy13 inp = mealy queue (0:>Nil) inp
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processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
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processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
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processingElement_mealy_diamond inp = mealy processingElement (1,(4,6,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,6,6)) inp
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prop4 (inp1,inp2) = queue_mealy13 (processingElement_mealy_or (bundle (queue_mealy11 (processingElement_mealy_not (bundle (inp1,inp1)) ), queue_mealy12 (processingElement_mealy_diamond (bundle (inp2,inp2)) ) )) )
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topEntity
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:: Clock System
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-> Reset System
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-> Enable System
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-> (Signal System (Bool), Signal System (Bool))
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-> Signal System ( Bool)
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topEntity = exposeClockResetEnable prop4
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testBench :: Signal System Bool
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testBench = done
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where
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testInput1 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, True, False, False, False, False, False, False, False, False, False, False, False, False])
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testInput2 = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False, True, True, True, True, True, True, True,False, False, False])
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expectOutput = outputVerifier' clk rst $(listToVecTH [False::Bool , False, False, False, False, False, False,False, True, True, True, True, True, True, True,False, False, False])
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done = expectOutput (topEntity clk rst en (testInput1, testInput2))
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en = enableGen
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clk = tbSystemClockGen (not <$> done)
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rst = systemResetGen
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