44 lines
2.3 KiB
Haskell
44 lines
2.3 KiB
Haskell
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module Operators where
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import Clash.Explicit.Testbench
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import Clash.Prelude
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import ProcessingElement(processingElement)
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import Queue(queue,queuetest)
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f (x,y) = x
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g (x,y) = y
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queue_mealy1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
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queue_mealy2 inp = mealy queuetest (0:>0:>0:>0:>0:>0:>Nil) inp
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queue_mealy3 inp = mealy queuetest (0:>Nil) inp
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processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
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or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1, inp2)))
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processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
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not_out inp1 =queue_mealy3 (processingElement_mealy_not (bundle ( inp1, inp1)))
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processingElement_mealy_box inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp
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box_out inp1 =queue_mealy2 (processingElement_mealy_box (bundle ( inp1, inp1)))
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processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp
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diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1, inp2)))
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--topEntity
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-- :: Clock System
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-- -> Reset System
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-- -> Enable System
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-- -> (Signal System (Bool))
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-- -> Signal System (Vec 6 (Signed 2), Bool)
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--topEntity = exposeClockResetEnable box_out
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--testBench :: Signal System Bool
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--testBench = done
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-- where
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-- testInput1 = stimuliGenerator clk rst $(listToVecTH [True::Bool , False, False, False, False, True, False, False, True, True, True, True, False])
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-- testInput2 = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False])
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-- expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)])
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-- done = expectOutput (topEntity clk rst en (testInput1, testInput2))
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-- en = enableGen
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-- clk = tbSystemClockGen (not <$> done)
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-- rst = systemResetGen
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