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No commits in common. "2b47f19f2023017f9e80fbfe632bfa5dde812bf8" and "5067f033226cbc0b923f019f93a55bc0eb5381dc" have entirely different histories.

34 changed files with 16 additions and 328594 deletions

24
.gitignore vendored
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@ -1,25 +1 @@
*.zip *.zip
# Compiled class file
*.class
# Log file
*.log
# BlueJ files
*.ctxt
# Mobile Tools for Java (J2ME)
.mtj.tmp/
# Package Files #
*.jar
*.war
*.nar
*.ear
*.zip
*.tar.gz
*.rar
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid*
replay_pid*

Binary file not shown.

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@ -1,8 +1,5 @@
package generic; package generic;
import java.io.FileInputStream;
import java.io.InputStream;
import processor.Clock; import processor.Clock;
import processor.Processor; import processor.Processor;
@ -22,6 +19,7 @@ public class Simulator {
static void loadProgram(String assemblyProgramFile) static void loadProgram(String assemblyProgramFile)
{ {
/* /*
* TODO
* 1. load the program into memory according to the program layout described * 1. load the program into memory according to the program layout described
* in the ISA specification * in the ISA specification
* 2. set PC to the address of the first instruction in the main * 2. set PC to the address of the first instruction in the main
@ -30,37 +28,6 @@ public class Simulator {
* x1 = 65535 * x1 = 65535
* x2 = 65535 * x2 = 65535
*/ */
try (
InputStream is = new FileInputStream(assemblyProgramFile);
){
int i = 0;
byte[] line = new byte[4];
boolean isFirstLine = true;
while(is.read(line) != -1) {
int value = 0;
for(int j = 0; j < 4; j++) {
value = (value << 8) | (line[j] & 0xff);
}
System.out.println(value);
if(isFirstLine) {
processor.getRegisterFile().setProgramCounter(value);
isFirstLine = false;
}else{
processor.getMainMemory().setWord(i, value);
i++;
}
}
processor.getRegisterFile().setValue(0, 0);
processor.getRegisterFile().setValue(1, 65535);
processor.getRegisterFile().setValue(2, 65535);
// Debug
System.out.println(processor.getRegisterFile().getProgramCounter());
System.out.println(processor.getMainMemory().getContentsAsString(0, 10));
} catch (Exception e) {
e.printStackTrace();
}
} }
public static void simulate() public static void simulate()
@ -77,8 +44,6 @@ public class Simulator {
Clock.incrementClock(); Clock.incrementClock();
processor.getRWUnit().performRW(); processor.getRWUnit().performRW();
Clock.incrementClock(); Clock.incrementClock();
Statistics.setNumberOfInstructions(Statistics.getNumberOfInstructions() + 1);
Statistics.setNumberOfCycles(Statistics.getNumberOfCycles() + 1);
} }
// TODO // TODO

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@ -27,22 +27,13 @@ public class Statistics {
Misc.printErrorAndExit(e.getMessage()); Misc.printErrorAndExit(e.getMessage());
} }
} }
// TODO write functions to update statistics
public static int getNumberOfInstructions() // TODO write functions to update statistics
{ public void setNumberOfInstructions(int numberOfInstructions) {
return numberOfInstructions;
}
public static int getNumberOfCycles()
{
return numberOfCycles;
}
public static void setNumberOfInstructions(int numberOfInstructions)
{
Statistics.numberOfInstructions = numberOfInstructions; Statistics.numberOfInstructions = numberOfInstructions;
} }
public static void setNumberOfCycles(int numberOfCycles) {
public void setNumberOfCycles(int numberOfCycles) {
Statistics.numberOfCycles = numberOfCycles; Statistics.numberOfCycles = numberOfCycles;
} }
} }

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@ -1,27 +1,10 @@
package processor.pipeline; package processor.pipeline;
public class EX_IF_LatchType { public class EX_IF_LatchType {
int pc;
boolean IF_enable;
public EX_IF_LatchType() public EX_IF_LatchType()
{ {
IF_enable = false;
} }
public boolean isIF_enable() {
return IF_enable;
}
public void setIF_enable(boolean iF_enable) {
IF_enable = iF_enable;
}
public int getPC() {
return pc;
}
public void setPC(int pc) {
this.pc = pc;
}
} }

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@ -1,44 +1,14 @@
package processor.pipeline; package processor.pipeline;
import generic.Instruction;
import generic.Operand;
public class EX_MA_LatchType { public class EX_MA_LatchType {
boolean MA_enable; boolean MA_enable;
Operand op2;
Instruction instruction;
int aluResult;
public EX_MA_LatchType() public EX_MA_LatchType()
{ {
MA_enable = false; MA_enable = false;
} }
public void setInstruction(Instruction instruction) {
this.instruction = instruction;
}
public Instruction getInstruction() {
return instruction;
}
public void setOp2(Operand op2) {
this.op2 = op2;
}
public Operand getOp2(){
return op2;
}
public void setALUResult(int aluResult) {
this.aluResult = aluResult;
}
public int getALUResult(){
return aluResult;
}
public boolean isMA_enable() { public boolean isMA_enable() {
return MA_enable; return MA_enable;
} }

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@ -1,9 +1,6 @@
package processor.pipeline; package processor.pipeline;
import processor.Processor; import processor.Processor;
import generic.Instruction;
import generic.Instruction.OperationType;
import generic.Simulator;
import generic.Operand.OperandType;
public class Execute { public class Execute {
Processor containingProcessor; Processor containingProcessor;
@ -22,106 +19,6 @@ public class Execute {
public void performEX() public void performEX()
{ {
//TODO //TODO
if(OF_EX_Latch.isEX_enable())
{
int op1 = OF_EX_Latch.getOp1();
int op2 = OF_EX_Latch.getOp2();
int imm = OF_EX_Latch.getImm();
Instruction instruction = OF_EX_Latch.getInstruction();
int cur_pc = containingProcessor.getRegisterFile().getProgramCounter();
int alu_result = 0;
OperationType alu_op = OF_EX_Latch.getInstruction().getOperationType();
switch(alu_op)
{
case add: alu_result = op1 + op2; break;
case addi: alu_result = op1 + imm; break;
case sub: alu_result = op1 - op2; break;
case subi: alu_result = op1 - imm; break;
case mul: alu_result = op1 * op2; break;
case muli: alu_result = op1 * imm; break;
case div: alu_result = op1 / op2; break;
case divi: alu_result = op1 / imm; break;
case and: alu_result = op1 & op2; break;
case andi: alu_result = op1 & imm; break;
case or: alu_result = op1 | op2; break;
case ori: alu_result = op1 | imm; break;
case xor: alu_result = op1 ^ op2; break;
case xori: alu_result = op1 ^ imm; break;
case slt: alu_result= (op1 < op2) ? 1 : 0; break;
case slti: alu_result= (op1 < imm) ? 1 : 0; break;
case sll: alu_result = op1 << op2; break;
case slli: alu_result = op1 << imm; break;
case srl: alu_result = op1 >>> op2; break;
case srli: alu_result = op1 >>> imm; break;
case sra: alu_result = op1 >> op2; break;
case srai: alu_result = op1 >> imm; break;
case jmp:
{
OperandType optype = instruction.getDestinationOperand().getOperandType();
if (optype == OperandType.Register){
imm = containingProcessor.getRegisterFile().getValue(
instruction.getDestinationOperand().getValue());
} }
else{
imm = OF_EX_Latch.getImm();
}
alu_result = cur_pc + imm;
EX_IF_Latch.setIF_enable(true);
EX_IF_Latch.setPC(alu_result);
}
break;
case beq:
{
if(op1 == op2)
{
alu_result = cur_pc + imm;
EX_IF_Latch.setIF_enable(true);
EX_IF_Latch.setPC(alu_result);
}
}
break;
case bne:
{
if(op1 != op2)
{
alu_result = cur_pc + imm;
EX_IF_Latch.setIF_enable(true);
EX_IF_Latch.setPC(alu_result);
}
}
break;
case blt:
{
if(op1 < op2)
{
alu_result = cur_pc + imm;
EX_IF_Latch.setIF_enable(true);
EX_IF_Latch.setPC(alu_result);
}
}
break;
case bgt:
{
if(op1 > op2)
{
alu_result = cur_pc + imm;
EX_IF_Latch.setIF_enable(true);
EX_IF_Latch.setPC(alu_result);
}
}
break;
case end:
{
Simulator.setSimulationComplete(true);
}
default:
break;
} }
EX_MA_Latch.setALUResult(alu_result);
EX_MA_Latch.setInstruction(OF_EX_Latch.getInstruction());
EX_MA_Latch.setMA_enable(true);
OF_EX_Latch.setEX_enable(false);
}
}
}

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@ -1,18 +1,12 @@
package processor.pipeline; package processor.pipeline;
import generic.Instruction;
public class MA_RW_LatchType { public class MA_RW_LatchType {
boolean RW_enable; boolean RW_enable;
int aluResult;
int load_result;
Instruction instruction;
public MA_RW_LatchType() public MA_RW_LatchType()
{ {
RW_enable = false; RW_enable = false;
} }
public boolean isRW_enable() { public boolean isRW_enable() {
@ -23,27 +17,4 @@ public class MA_RW_LatchType {
RW_enable = rW_enable; RW_enable = rW_enable;
} }
public void setALU_result(int alu_result) {
this.aluResult = alu_result;
}
public int getALU_result() {
return aluResult;
}
public void setLoad_result(int load_result) {
this.load_result = load_result;
}
public int getLoad_result() {
return load_result;
}
public void setInstruction(Instruction instruction) {
this.instruction = instruction;
}
public Instruction getInstruction() {
return instruction;
}
} }

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@ -1,8 +1,6 @@
package processor.pipeline; package processor.pipeline;
import generic.Instruction;
import processor.Processor; import processor.Processor;
import generic.Instruction.OperationType;
public class MemoryAccess { public class MemoryAccess {
Processor containingProcessor; Processor containingProcessor;
@ -18,28 +16,7 @@ public class MemoryAccess {
public void performMA() public void performMA()
{ {
if(EX_MA_Latch.isMA_enable()) //TODO
{
Instruction instruction = EX_MA_Latch.getInstruction();
int alu_result = EX_MA_Latch.getALUResult();
MA_RW_Latch.setALU_result(alu_result);
OperationType op_type = instruction.getOperationType();
if (op_type==OperationType.store)
{
int val_store = containingProcessor.getRegisterFile().getValue(
instruction.getSourceOperand1().getValue());
containingProcessor.getMainMemory().setWord(alu_result, val_store);
}
else if (op_type==OperationType.load)
{
int load_result = containingProcessor.getMainMemory().getWord(alu_result);
MA_RW_Latch.setLoad_result(load_result);
}
MA_RW_Latch.setInstruction(instruction);
MA_RW_Latch.setRW_enable(true);
EX_MA_Latch.setMA_enable(false);
}
} }
} }

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@ -1,50 +1,14 @@
package processor.pipeline; package processor.pipeline;
import generic.Instruction;
public class OF_EX_LatchType { public class OF_EX_LatchType {
boolean EX_enable; boolean EX_enable;
Instruction instruction;
int op1, op2, imm;
public OF_EX_LatchType() public OF_EX_LatchType()
{ {
EX_enable = false; EX_enable = false;
} }
public void setInstruction(Instruction instruction) {
this.instruction = instruction;
}
public Instruction getInstruction() {
return instruction;
}
public void setOp1(int op1) {
this.op1 = op1;
}
public int getOp1() {
return op1;
}
public void setOp2(int op2) {
this.op2 = op2;
}
public int getOp2() {
return op2;
}
public void setImm(int imm) {
this.imm = imm;
}
public int getImm() {
return imm;
}
public boolean isEX_enable() { public boolean isEX_enable() {
return EX_enable; return EX_enable;
} }
@ -53,5 +17,4 @@ public class OF_EX_LatchType {
EX_enable = eX_enable; EX_enable = eX_enable;
} }
} }

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@ -1,17 +1,11 @@
package processor.pipeline; package processor.pipeline;
import java.util.Arrays;
import generic.Instruction;
import processor.Processor; import processor.Processor;
import generic.Instruction.OperationType;
import generic.Operand;
public class OperandFetch { public class OperandFetch {
Processor containingProcessor; Processor containingProcessor;
IF_OF_LatchType IF_OF_Latch; IF_OF_LatchType IF_OF_Latch;
OF_EX_LatchType OF_EX_Latch; OF_EX_LatchType OF_EX_Latch;
static OperationType[] opTypes = OperationType.values();
public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch) public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch)
{ {
@ -24,79 +18,7 @@ public class OperandFetch {
{ {
if(IF_OF_Latch.isOF_enable()) if(IF_OF_Latch.isOF_enable())
{ {
int instruction = IF_OF_Latch.getInstruction(); //TODO
Instruction instr = new Instruction();
String bin_instr = Integer.toBinaryString(instruction);
int opcode = Integer.parseInt(bin_instr.substring(0, 5), 2);
instr.setOperationType(opTypes[opcode]);
int R3_type_operators[] = {0,2,4,6,8,10,12,14,16,18,20};
int R2I_type_operators[] = {1,3,5,7,9,11,13,15,17,19,21,22,23,25,26,27,28};
int R1I_type_operators[] = {24,29};
// if (bin_instr.length() < 32) { // TODO: check if this is correct
// int diff = 32 - bin_instr.length();
// String zeros = "";
// for (int i = 0; i < diff; i++) {
// zeros += "0";
// }
// bin_instr = zeros + bin_instr;
// }
if (Arrays.asList(R3_type_operators).contains(opcode)){
Operand rs1 = new Operand();
Operand rs2 = new Operand();
Operand rd = new Operand();
rs1.setOperandType(Operand.OperandType.Register);
rs2.setOperandType(Operand.OperandType.Register);
rd.setOperandType(Operand.OperandType.Register);
rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
rs2.setValue(Integer.parseInt(bin_instr.substring(9, 14), 2));
rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2));
int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue());
int op2 = containingProcessor.getRegisterFile().getValue(rs2.getValue());
OF_EX_Latch.setInstruction(instr);
OF_EX_Latch.setOp1(op1);
OF_EX_Latch.setOp2(op2);
instr.setDestinationOperand(rd);
instr.setSourceOperand1(rs1);
instr.setSourceOperand2(rs2);
}
else if (Arrays.asList(R2I_type_operators).contains(opcode)){
Operand rs1 = new Operand();
Operand rd = new Operand();
rs1.setOperandType(Operand.OperandType.Register);
rd.setOperandType(Operand.OperandType.Register);
rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2));
int imm = Integer.parseInt(bin_instr.substring(19, 32), 2); // TODO: 2's complement
int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue());
OF_EX_Latch.setInstruction(instr);
OF_EX_Latch.setImm(imm);
OF_EX_Latch.setOp1(op1);
instr.setDestinationOperand(rd);
instr.setSourceOperand1(rs1);
}
else if (Arrays.asList(R1I_type_operators).contains(opcode)){
Operand rd = new Operand();
rd.setOperandType(Operand.OperandType.Register);
rd.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
instr.setDestinationOperand(rd);
int imm = Integer.parseInt(bin_instr.substring(10, 32), 2); // TODO: 2's complement
OF_EX_Latch.setInstruction(instr);
OF_EX_Latch.setImm(imm);
}
IF_OF_Latch.setOF_enable(false); IF_OF_Latch.setOF_enable(false);
OF_EX_Latch.setEX_enable(true); OF_EX_Latch.setEX_enable(true);

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@ -2,8 +2,6 @@ package processor.pipeline;
import generic.Simulator; import generic.Simulator;
import processor.Processor; import processor.Processor;
import generic.Instruction;
import generic.Instruction.OperationType;
public class RegisterWrite { public class RegisterWrite {
Processor containingProcessor; Processor containingProcessor;
@ -21,29 +19,10 @@ public class RegisterWrite {
{ {
if(MA_RW_Latch.isRW_enable()) if(MA_RW_Latch.isRW_enable())
{ {
Instruction instruction = MA_RW_Latch.getInstruction(); //TODO
OperationType op_type = instruction.getOperationType();
int alu_result = MA_RW_Latch.getALU_result(); // if instruction being processed is an end instruction, remember to call Simulator.setSimulationComplete(true);
if (op_type==OperationType.load)
{
int load_result = MA_RW_Latch.getLoad_result();
int rd = instruction.getDestinationOperand().getValue();
containingProcessor.getRegisterFile().setValue(rd, load_result);
}
else if (op_type==OperationType.end)
{
Simulator.setSimulationComplete(true);
}
else
{
if (op_type!=OperationType.store && op_type!= OperationType.jmp && op_type!= OperationType.beq && op_type!=OperationType.bne && op_type!=OperationType.blt && op_type!=OperationType.bgt)
{
int rd = instruction.getDestinationOperand().getValue();
rd = instruction.getDestinationOperand().getValue();
containingProcessor.getRegisterFile().setValue(rd, alu_result);
}
}
MA_RW_Latch.setRW_enable(false); MA_RW_Latch.setRW_enable(false);
IF_EnableLatch.setIF_enable(true); IF_EnableLatch.setIF_enable(true);
} }

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@ -1,39 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- WARNING: Eclipse auto-generated file.
Any modifications will be overwritten.
To include a user specific buildfile here, simply create one in the same
directory with the processing instruction <?eclipse.ant.import?>
as the first entry and export the buildfile again. --><project basedir="." default="build">
<property environment="env"/>
<property name="debuglevel" value="source,lines,vars"/>
<property name="target" value="1.8"/>
<property name="source" value="1.8"/>
<target name="init">
<mkdir dir="bin"/>
<copy includeemptydirs="false" todir="bin">
<fileset dir="src">
<exclude name="**/*.launch"/>
<exclude name="**/*.java"/>
</fileset>
</copy>
</target>
<target name="clean">
<delete dir="bin"/>
</target>
<target depends="clean" name="cleanall"/>
<target depends="build-subprojects,build-project" name="build"/>
<target name="build-subprojects"/>
<target depends="init" name="build-project">
<javac debug="true" debuglevel="${debuglevel}" destdir="bin" includeantruntime="false" source="${source}" target="${target}">
<src path="src"/>
</javac>
</target>
<target name="make-jar" depends="build">
<mkdir dir="jars"/>
<jar destfile="jars/simulator.jar" basedir="bin">
<manifest>
<attribute name="Main-Class" value="main.Main"/>
</manifest>
</jar>
</target>
</project>

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@ -1,40 +0,0 @@
.data
a:
40
20
50
60
80
30
10
70
n:
8
.text
main:
sub %x3, %x3, %x3
sub %x4, %x4, %x4
load %x0, $n, %x8
outerloop:
blt %x3, %x8, innerloop
end
addi %x3, 1, %x4
innerloop:
addi %x3, 1, %x4
innerloopz:
blt %x4, %x8, swap
addi %3, 1, %x3
jmp outerloop
swap:
load %x3, $a, %x5
load %x4, $a, %x6
blt %x5, %x6, exchange
addi %x4, 1, %x4
jmp innerloopz
exchange:
sub %x7, %x7, %x7
add %x0, %x5, %x7
store %x6, 0, %x3
store %x7, 0, %x4
addi %x4, 1, %x4
jmp innerloopz

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@ -1 +0,0 @@
Hash of the Processor State = 255541867

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@ -1,15 +0,0 @@
.data
n:
11
.text
main:
load %x0, $n, %x3
divi %x3, 2, %x3
beq %x0, %x31, even
sub %x10, %x10, %x10
addi %x10, 1, %x10
end
even:
sub %x10, $x10, %x10
subi %x10, 1, %x10
end

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@ -1 +0,0 @@
Hash of the Processor State = -224294686

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@ -1,28 +0,0 @@
.data
n:
10
.text
main:
addi %x0, 0, %x3
addi %x0, 1, %x4
add %x3, %x4, %x5
load %x0, $n, %x6
addi %x0, 65535, %x7
addi %x0, 0, %x8
store %x3, 0, %x7
subi %x7, 1, %x7
addi %x8, 1, %x8
store %x4, 0, %x7
subi %x7, 1, %x7
addi %x8, 1, %x8
for:
blt %x8, %x6, loop
end
loop:
add %x3, %x4, %x5
store %x5, 0, %x7
subi %x7, 1, %x7
addi %x8, 1, %x8
add %x0, %x4, %x3
add %x0, %x5, %x4
jmp for

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@ -1 +0,0 @@
Hash of the Processor State = -1518357572

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@ -1,23 +0,0 @@
.data
a:
4567654
.text
main:
load %x0, $a, %x3
sub %x7, %x7, %x7
loop:
divi %x3, 10, %x4
addi %x31, 0, %x30
muli %x7, 10, %x7
add %x7, %x30, %x7
divi %x3, 10, %x3
bgt %x3, %x0, loop
load %x0, $a, %x5
beq %x5, %x7, palindrome
sub %x10, %x10, %x10
subi %x10, 1, %x10
end
palindrome:
sub %x10, %x10, %x10
addi %x10, 1, %x10
end

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@ -1,2 +0,0 @@
Hash of the Processor State = 155317940

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@ -1,24 +0,0 @@
.data
a:
11
.text
main:
load %x0, $a, %x3
sub %x4, %x4, %x4
divi %x3, 2, %x4
sub %x6, %x6, %x6
addi %x6, 2, %x6
for:
bgt %x6, %x4, prime
div %x3, %x6, %x7
beq %x0, %x31, notprime
addi %x6, 1, %x6
jmp for
prime:
sub %x10, %x10, %x10
addi %x10, 1, %x10
end
notprime:
sub %x10, %x10, %x10
subi %x10, 1, %x10
end

File diff suppressed because it is too large Load Diff

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@ -1 +0,0 @@
Hash of the Processor State = -1414219998

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@ -1,92 +0,0 @@
#!/bin/python
import sys
import os
import zipfile
import shutil
import subprocess
from threading import Timer
zip_file = sys.argv[1]
l = len(zip_file.split("/"))
print "Students :"
for i in range(0, len(zip_file.split("/")[l-1].split("_"))):
print zip_file.split("/")[l-1].split("_")[i].split(".")[0]
print ""
submissions_temp_dir = "./submissions/"
if not os.path.exists(submissions_temp_dir):
os.mkdir(submissions_temp_dir)
zip_ref = zipfile.ZipFile(zip_file, 'r')
zip_ref.extractall(submissions_temp_dir)
zip_ref.close()
shutil.copyfile("build.xml", submissions_temp_dir + "/build.xml")
os.chdir(submissions_temp_dir)
stdout_file = open("./tmp.output", 'a')
popen_args = ["ant", "make-jar"]
proc = subprocess.Popen(popen_args, stdout = stdout_file, stderr = stdout_file)
timer = Timer(5, proc.kill)
try:
timer.start()
stdout, stderr = proc.communicate()
finally:
timer.cancel()
stdout_file.close()
if not os.path.exists("jars/simulator.jar"):
print "compilation failed. jar file not created"
sys.exit(0)
test_cases_dir = "../test_cases"
total_marks = 0
scored_marks = 0
for testcase in os.listdir(test_cases_dir):
if ".out" in testcase:
total_marks = total_marks + 1
stdout_file = open("./" + testcase.split(".")[0] + ".observedoutput", 'w')
popen_args = ["java", "-Xmx1g", "-jar", "jars/simulator.jar", "./src/configuration/config.xml", "./" + testcase.split(".")[0] + ".observedstat", test_cases_dir + "/" + testcase]
# print popen_args
proc = subprocess.Popen(popen_args, stdout = stdout_file, stderr = stdout_file)
timer = Timer(5, proc.kill)
try:
timer.start()
stdout, stderr = proc.communicate()
finally:
timer.cancel()
stdout_file.close()
if os.path.exists("./" + testcase.split(".")[0] + ".observedoutput"):
expectedoutput_file = open(test_cases_dir + "/" + testcase.split(".")[0] + ".expected")
expected_hash = expectedoutput_file.readline()
expectedoutput_file.close()
correct = False
observedoutput_file = open("./" + testcase.split(".")[0] + ".observedoutput")
for line in observedoutput_file:
# if "Hash" in line:
# print "computed = " + line
# print "expected = " + expected_hash
if line == expected_hash:
correct = True
break
observedoutput_file.close()
if correct == True:
scored_marks = scored_marks + 1
print testcase + " : PASS!"
else:
print testcase + " : fail - incorrect hash"
else:
print testcase + " : fail - standard output file not created"
os.chdir("..")
shutil.rmtree(submissions_temp_dir)
print "\ntotal score = " + str(scored_marks) + " out of " + str(total_marks)