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No commits in common. "2b47f19f2023017f9e80fbfe632bfa5dde812bf8" and "5067f033226cbc0b923f019f93a55bc0eb5381dc" have entirely different histories.
2b47f19f20
...
5067f03322
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@ -1,25 +1 @@
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*.zip
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# Compiled class file
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*.class
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# Log file
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*.log
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# BlueJ files
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*.ctxt
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# Mobile Tools for Java (J2ME)
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.mtj.tmp/
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# Package Files #
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*.jar
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*.war
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*.nar
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*.ear
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*.zip
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*.tar.gz
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*.rar
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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replay_pid*
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*.zip
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Binary file not shown.
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@ -1,8 +1,5 @@
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package generic;
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import java.io.FileInputStream;
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import java.io.InputStream;
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import processor.Clock;
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import processor.Processor;
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@ -22,6 +19,7 @@ public class Simulator {
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static void loadProgram(String assemblyProgramFile)
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{
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/*
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* TODO
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* 1. load the program into memory according to the program layout described
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* in the ISA specification
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* 2. set PC to the address of the first instruction in the main
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@ -30,37 +28,6 @@ public class Simulator {
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* x1 = 65535
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* x2 = 65535
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*/
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try (
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InputStream is = new FileInputStream(assemblyProgramFile);
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){
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int i = 0;
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byte[] line = new byte[4];
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boolean isFirstLine = true;
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while(is.read(line) != -1) {
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int value = 0;
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for(int j = 0; j < 4; j++) {
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value = (value << 8) | (line[j] & 0xff);
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}
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System.out.println(value);
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if(isFirstLine) {
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processor.getRegisterFile().setProgramCounter(value);
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isFirstLine = false;
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}else{
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processor.getMainMemory().setWord(i, value);
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i++;
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}
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}
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processor.getRegisterFile().setValue(0, 0);
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processor.getRegisterFile().setValue(1, 65535);
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processor.getRegisterFile().setValue(2, 65535);
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// Debug
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System.out.println(processor.getRegisterFile().getProgramCounter());
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System.out.println(processor.getMainMemory().getContentsAsString(0, 10));
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} catch (Exception e) {
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e.printStackTrace();
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}
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}
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public static void simulate()
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@ -77,8 +44,6 @@ public class Simulator {
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Clock.incrementClock();
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processor.getRWUnit().performRW();
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Clock.incrementClock();
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Statistics.setNumberOfInstructions(Statistics.getNumberOfInstructions() + 1);
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Statistics.setNumberOfCycles(Statistics.getNumberOfCycles() + 1);
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}
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// TODO
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|
|
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@ -27,22 +27,13 @@ public class Statistics {
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Misc.printErrorAndExit(e.getMessage());
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}
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}
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// TODO write functions to update statistics
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public static int getNumberOfInstructions()
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{
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return numberOfInstructions;
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}
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public static int getNumberOfCycles()
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{
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return numberOfCycles;
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}
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public static void setNumberOfInstructions(int numberOfInstructions)
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{
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public void setNumberOfInstructions(int numberOfInstructions) {
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Statistics.numberOfInstructions = numberOfInstructions;
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}
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public static void setNumberOfCycles(int numberOfCycles) {
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public void setNumberOfCycles(int numberOfCycles) {
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Statistics.numberOfCycles = numberOfCycles;
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}
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}
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|
|
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@ -1,27 +1,10 @@
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package processor.pipeline;
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public class EX_IF_LatchType {
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int pc;
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boolean IF_enable;
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public EX_IF_LatchType()
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{
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IF_enable = false;
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}
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public boolean isIF_enable() {
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return IF_enable;
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}
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public void setIF_enable(boolean iF_enable) {
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IF_enable = iF_enable;
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}
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public int getPC() {
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return pc;
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}
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public void setPC(int pc) {
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this.pc = pc;
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}
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}
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|
|
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@ -1,44 +1,14 @@
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package processor.pipeline;
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import generic.Instruction;
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import generic.Operand;
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public class EX_MA_LatchType {
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boolean MA_enable;
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Operand op2;
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Instruction instruction;
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int aluResult;
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public EX_MA_LatchType()
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{
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MA_enable = false;
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}
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public void setInstruction(Instruction instruction) {
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this.instruction = instruction;
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}
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public Instruction getInstruction() {
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return instruction;
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}
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public void setOp2(Operand op2) {
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this.op2 = op2;
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}
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public Operand getOp2(){
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return op2;
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}
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public void setALUResult(int aluResult) {
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this.aluResult = aluResult;
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}
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public int getALUResult(){
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return aluResult;
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}
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public boolean isMA_enable() {
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return MA_enable;
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}
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|
|
|
@ -1,9 +1,6 @@
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package processor.pipeline;
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import processor.Processor;
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import generic.Instruction;
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import generic.Instruction.OperationType;
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import generic.Simulator;
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import generic.Operand.OperandType;
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public class Execute {
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Processor containingProcessor;
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|
@ -22,106 +19,6 @@ public class Execute {
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public void performEX()
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{
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//TODO
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if(OF_EX_Latch.isEX_enable())
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{
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int op1 = OF_EX_Latch.getOp1();
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int op2 = OF_EX_Latch.getOp2();
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int imm = OF_EX_Latch.getImm();
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Instruction instruction = OF_EX_Latch.getInstruction();
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int cur_pc = containingProcessor.getRegisterFile().getProgramCounter();
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int alu_result = 0;
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OperationType alu_op = OF_EX_Latch.getInstruction().getOperationType();
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switch(alu_op)
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{
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case add: alu_result = op1 + op2; break;
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case addi: alu_result = op1 + imm; break;
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case sub: alu_result = op1 - op2; break;
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case subi: alu_result = op1 - imm; break;
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case mul: alu_result = op1 * op2; break;
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case muli: alu_result = op1 * imm; break;
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case div: alu_result = op1 / op2; break;
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case divi: alu_result = op1 / imm; break;
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case and: alu_result = op1 & op2; break;
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case andi: alu_result = op1 & imm; break;
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case or: alu_result = op1 | op2; break;
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case ori: alu_result = op1 | imm; break;
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case xor: alu_result = op1 ^ op2; break;
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case xori: alu_result = op1 ^ imm; break;
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case slt: alu_result= (op1 < op2) ? 1 : 0; break;
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case slti: alu_result= (op1 < imm) ? 1 : 0; break;
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case sll: alu_result = op1 << op2; break;
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case slli: alu_result = op1 << imm; break;
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case srl: alu_result = op1 >>> op2; break;
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case srli: alu_result = op1 >>> imm; break;
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case sra: alu_result = op1 >> op2; break;
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case srai: alu_result = op1 >> imm; break;
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case jmp:
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{
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OperandType optype = instruction.getDestinationOperand().getOperandType();
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if (optype == OperandType.Register){
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imm = containingProcessor.getRegisterFile().getValue(
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instruction.getDestinationOperand().getValue());
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}
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else{
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imm = OF_EX_Latch.getImm();
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}
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alu_result = cur_pc + imm;
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EX_IF_Latch.setIF_enable(true);
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EX_IF_Latch.setPC(alu_result);
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}
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break;
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case beq:
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{
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if(op1 == op2)
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{
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alu_result = cur_pc + imm;
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EX_IF_Latch.setIF_enable(true);
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EX_IF_Latch.setPC(alu_result);
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}
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}
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break;
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case bne:
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{
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if(op1 != op2)
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{
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alu_result = cur_pc + imm;
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EX_IF_Latch.setIF_enable(true);
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EX_IF_Latch.setPC(alu_result);
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}
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}
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break;
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case blt:
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{
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if(op1 < op2)
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{
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alu_result = cur_pc + imm;
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EX_IF_Latch.setIF_enable(true);
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EX_IF_Latch.setPC(alu_result);
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}
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}
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break;
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case bgt:
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{
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if(op1 > op2)
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{
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alu_result = cur_pc + imm;
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EX_IF_Latch.setIF_enable(true);
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EX_IF_Latch.setPC(alu_result);
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}
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}
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break;
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case end:
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{
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Simulator.setSimulationComplete(true);
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}
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default:
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break;
|
||||
|
||||
}
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EX_MA_Latch.setALUResult(alu_result);
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EX_MA_Latch.setInstruction(OF_EX_Latch.getInstruction());
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EX_MA_Latch.setMA_enable(true);
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||||
OF_EX_Latch.setEX_enable(false);
|
||||
}
|
||||
}
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||||
|
||||
}
|
||||
|
|
|
@ -1,18 +1,12 @@
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|||
package processor.pipeline;
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||||
|
||||
import generic.Instruction;
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||||
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||||
public class MA_RW_LatchType {
|
||||
|
||||
boolean RW_enable;
|
||||
int aluResult;
|
||||
int load_result;
|
||||
Instruction instruction;
|
||||
|
||||
|
||||
public MA_RW_LatchType()
|
||||
{
|
||||
RW_enable = false;
|
||||
|
||||
}
|
||||
|
||||
public boolean isRW_enable() {
|
||||
|
@ -23,27 +17,4 @@ public class MA_RW_LatchType {
|
|||
RW_enable = rW_enable;
|
||||
}
|
||||
|
||||
public void setALU_result(int alu_result) {
|
||||
this.aluResult = alu_result;
|
||||
}
|
||||
|
||||
public int getALU_result() {
|
||||
return aluResult;
|
||||
}
|
||||
|
||||
public void setLoad_result(int load_result) {
|
||||
this.load_result = load_result;
|
||||
}
|
||||
|
||||
public int getLoad_result() {
|
||||
return load_result;
|
||||
}
|
||||
|
||||
public void setInstruction(Instruction instruction) {
|
||||
this.instruction = instruction;
|
||||
}
|
||||
|
||||
public Instruction getInstruction() {
|
||||
return instruction;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,8 +1,6 @@
|
|||
package processor.pipeline;
|
||||
|
||||
import generic.Instruction;
|
||||
import processor.Processor;
|
||||
import generic.Instruction.OperationType;
|
||||
|
||||
public class MemoryAccess {
|
||||
Processor containingProcessor;
|
||||
|
@ -18,28 +16,7 @@ public class MemoryAccess {
|
|||
|
||||
public void performMA()
|
||||
{
|
||||
if(EX_MA_Latch.isMA_enable())
|
||||
{
|
||||
Instruction instruction = EX_MA_Latch.getInstruction();
|
||||
int alu_result = EX_MA_Latch.getALUResult();
|
||||
MA_RW_Latch.setALU_result(alu_result);
|
||||
OperationType op_type = instruction.getOperationType();
|
||||
if (op_type==OperationType.store)
|
||||
{
|
||||
int val_store = containingProcessor.getRegisterFile().getValue(
|
||||
instruction.getSourceOperand1().getValue());
|
||||
containingProcessor.getMainMemory().setWord(alu_result, val_store);
|
||||
}
|
||||
else if (op_type==OperationType.load)
|
||||
{
|
||||
int load_result = containingProcessor.getMainMemory().getWord(alu_result);
|
||||
MA_RW_Latch.setLoad_result(load_result);
|
||||
}
|
||||
MA_RW_Latch.setInstruction(instruction);
|
||||
MA_RW_Latch.setRW_enable(true);
|
||||
EX_MA_Latch.setMA_enable(false);
|
||||
|
||||
}
|
||||
//TODO
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
@ -1,50 +1,14 @@
|
|||
package processor.pipeline;
|
||||
|
||||
import generic.Instruction;
|
||||
|
||||
public class OF_EX_LatchType {
|
||||
|
||||
boolean EX_enable;
|
||||
Instruction instruction;
|
||||
int op1, op2, imm;
|
||||
|
||||
public OF_EX_LatchType()
|
||||
{
|
||||
EX_enable = false;
|
||||
}
|
||||
|
||||
public void setInstruction(Instruction instruction) {
|
||||
this.instruction = instruction;
|
||||
}
|
||||
|
||||
public Instruction getInstruction() {
|
||||
return instruction;
|
||||
}
|
||||
|
||||
public void setOp1(int op1) {
|
||||
this.op1 = op1;
|
||||
}
|
||||
|
||||
public int getOp1() {
|
||||
return op1;
|
||||
}
|
||||
|
||||
public void setOp2(int op2) {
|
||||
this.op2 = op2;
|
||||
}
|
||||
|
||||
public int getOp2() {
|
||||
return op2;
|
||||
}
|
||||
|
||||
public void setImm(int imm) {
|
||||
this.imm = imm;
|
||||
}
|
||||
|
||||
public int getImm() {
|
||||
return imm;
|
||||
}
|
||||
|
||||
public boolean isEX_enable() {
|
||||
return EX_enable;
|
||||
}
|
||||
|
@ -53,5 +17,4 @@ public class OF_EX_LatchType {
|
|||
EX_enable = eX_enable;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
|
|
@ -1,17 +1,11 @@
|
|||
package processor.pipeline;
|
||||
|
||||
import java.util.Arrays;
|
||||
|
||||
import generic.Instruction;
|
||||
import processor.Processor;
|
||||
import generic.Instruction.OperationType;
|
||||
import generic.Operand;
|
||||
|
||||
public class OperandFetch {
|
||||
Processor containingProcessor;
|
||||
IF_OF_LatchType IF_OF_Latch;
|
||||
OF_EX_LatchType OF_EX_Latch;
|
||||
static OperationType[] opTypes = OperationType.values();
|
||||
|
||||
public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch)
|
||||
{
|
||||
|
@ -24,80 +18,8 @@ public class OperandFetch {
|
|||
{
|
||||
if(IF_OF_Latch.isOF_enable())
|
||||
{
|
||||
int instruction = IF_OF_Latch.getInstruction();
|
||||
Instruction instr = new Instruction();
|
||||
String bin_instr = Integer.toBinaryString(instruction);
|
||||
int opcode = Integer.parseInt(bin_instr.substring(0, 5), 2);
|
||||
instr.setOperationType(opTypes[opcode]);
|
||||
//TODO
|
||||
|
||||
int R3_type_operators[] = {0,2,4,6,8,10,12,14,16,18,20};
|
||||
int R2I_type_operators[] = {1,3,5,7,9,11,13,15,17,19,21,22,23,25,26,27,28};
|
||||
int R1I_type_operators[] = {24,29};
|
||||
|
||||
// if (bin_instr.length() < 32) { // TODO: check if this is correct
|
||||
// int diff = 32 - bin_instr.length();
|
||||
// String zeros = "";
|
||||
// for (int i = 0; i < diff; i++) {
|
||||
// zeros += "0";
|
||||
// }
|
||||
// bin_instr = zeros + bin_instr;
|
||||
// }
|
||||
|
||||
if (Arrays.asList(R3_type_operators).contains(opcode)){
|
||||
Operand rs1 = new Operand();
|
||||
Operand rs2 = new Operand();
|
||||
Operand rd = new Operand();
|
||||
rs1.setOperandType(Operand.OperandType.Register);
|
||||
rs2.setOperandType(Operand.OperandType.Register);
|
||||
rd.setOperandType(Operand.OperandType.Register);
|
||||
|
||||
rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
|
||||
rs2.setValue(Integer.parseInt(bin_instr.substring(9, 14), 2));
|
||||
rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2));
|
||||
|
||||
int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue());
|
||||
int op2 = containingProcessor.getRegisterFile().getValue(rs2.getValue());
|
||||
|
||||
OF_EX_Latch.setInstruction(instr);
|
||||
OF_EX_Latch.setOp1(op1);
|
||||
OF_EX_Latch.setOp2(op2);
|
||||
instr.setDestinationOperand(rd);
|
||||
instr.setSourceOperand1(rs1);
|
||||
instr.setSourceOperand2(rs2);
|
||||
}
|
||||
else if (Arrays.asList(R2I_type_operators).contains(opcode)){
|
||||
Operand rs1 = new Operand();
|
||||
Operand rd = new Operand();
|
||||
rs1.setOperandType(Operand.OperandType.Register);
|
||||
rd.setOperandType(Operand.OperandType.Register);
|
||||
|
||||
rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
|
||||
rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2));
|
||||
|
||||
int imm = Integer.parseInt(bin_instr.substring(19, 32), 2); // TODO: 2's complement
|
||||
|
||||
int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue());
|
||||
|
||||
OF_EX_Latch.setInstruction(instr);
|
||||
OF_EX_Latch.setImm(imm);
|
||||
OF_EX_Latch.setOp1(op1);
|
||||
|
||||
instr.setDestinationOperand(rd);
|
||||
instr.setSourceOperand1(rs1);
|
||||
}
|
||||
else if (Arrays.asList(R1I_type_operators).contains(opcode)){
|
||||
Operand rd = new Operand();
|
||||
rd.setOperandType(Operand.OperandType.Register);
|
||||
rd.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2));
|
||||
|
||||
instr.setDestinationOperand(rd);
|
||||
|
||||
int imm = Integer.parseInt(bin_instr.substring(10, 32), 2); // TODO: 2's complement
|
||||
|
||||
OF_EX_Latch.setInstruction(instr);
|
||||
OF_EX_Latch.setImm(imm);
|
||||
}
|
||||
|
||||
IF_OF_Latch.setOF_enable(false);
|
||||
OF_EX_Latch.setEX_enable(true);
|
||||
}
|
||||
|
|
|
@ -2,8 +2,6 @@ package processor.pipeline;
|
|||
|
||||
import generic.Simulator;
|
||||
import processor.Processor;
|
||||
import generic.Instruction;
|
||||
import generic.Instruction.OperationType;
|
||||
|
||||
public class RegisterWrite {
|
||||
Processor containingProcessor;
|
||||
|
@ -21,29 +19,10 @@ public class RegisterWrite {
|
|||
{
|
||||
if(MA_RW_Latch.isRW_enable())
|
||||
{
|
||||
Instruction instruction = MA_RW_Latch.getInstruction();
|
||||
OperationType op_type = instruction.getOperationType();
|
||||
int alu_result = MA_RW_Latch.getALU_result();
|
||||
|
||||
if (op_type==OperationType.load)
|
||||
{
|
||||
int load_result = MA_RW_Latch.getLoad_result();
|
||||
int rd = instruction.getDestinationOperand().getValue();
|
||||
containingProcessor.getRegisterFile().setValue(rd, load_result);
|
||||
}
|
||||
else if (op_type==OperationType.end)
|
||||
{
|
||||
Simulator.setSimulationComplete(true);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (op_type!=OperationType.store && op_type!= OperationType.jmp && op_type!= OperationType.beq && op_type!=OperationType.bne && op_type!=OperationType.blt && op_type!=OperationType.bgt)
|
||||
{
|
||||
int rd = instruction.getDestinationOperand().getValue();
|
||||
rd = instruction.getDestinationOperand().getValue();
|
||||
containingProcessor.getRegisterFile().setValue(rd, alu_result);
|
||||
}
|
||||
}
|
||||
//TODO
|
||||
|
||||
// if instruction being processed is an end instruction, remember to call Simulator.setSimulationComplete(true);
|
||||
|
||||
MA_RW_Latch.setRW_enable(false);
|
||||
IF_EnableLatch.setIF_enable(true);
|
||||
}
|
||||
|
|
|
@ -1,39 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!-- WARNING: Eclipse auto-generated file.
|
||||
Any modifications will be overwritten.
|
||||
To include a user specific buildfile here, simply create one in the same
|
||||
directory with the processing instruction <?eclipse.ant.import?>
|
||||
as the first entry and export the buildfile again. --><project basedir="." default="build">
|
||||
<property environment="env"/>
|
||||
<property name="debuglevel" value="source,lines,vars"/>
|
||||
<property name="target" value="1.8"/>
|
||||
<property name="source" value="1.8"/>
|
||||
<target name="init">
|
||||
<mkdir dir="bin"/>
|
||||
<copy includeemptydirs="false" todir="bin">
|
||||
<fileset dir="src">
|
||||
<exclude name="**/*.launch"/>
|
||||
<exclude name="**/*.java"/>
|
||||
</fileset>
|
||||
</copy>
|
||||
</target>
|
||||
<target name="clean">
|
||||
<delete dir="bin"/>
|
||||
</target>
|
||||
<target depends="clean" name="cleanall"/>
|
||||
<target depends="build-subprojects,build-project" name="build"/>
|
||||
<target name="build-subprojects"/>
|
||||
<target depends="init" name="build-project">
|
||||
<javac debug="true" debuglevel="${debuglevel}" destdir="bin" includeantruntime="false" source="${source}" target="${target}">
|
||||
<src path="src"/>
|
||||
</javac>
|
||||
</target>
|
||||
<target name="make-jar" depends="build">
|
||||
<mkdir dir="jars"/>
|
||||
<jar destfile="jars/simulator.jar" basedir="bin">
|
||||
<manifest>
|
||||
<attribute name="Main-Class" value="main.Main"/>
|
||||
</manifest>
|
||||
</jar>
|
||||
</target>
|
||||
</project>
|
|
@ -1,40 +0,0 @@
|
|||
.data
|
||||
a:
|
||||
40
|
||||
20
|
||||
50
|
||||
60
|
||||
80
|
||||
30
|
||||
10
|
||||
70
|
||||
n:
|
||||
8
|
||||
.text
|
||||
main:
|
||||
sub %x3, %x3, %x3
|
||||
sub %x4, %x4, %x4
|
||||
load %x0, $n, %x8
|
||||
outerloop:
|
||||
blt %x3, %x8, innerloop
|
||||
end
|
||||
addi %x3, 1, %x4
|
||||
innerloop:
|
||||
addi %x3, 1, %x4
|
||||
innerloopz:
|
||||
blt %x4, %x8, swap
|
||||
addi %3, 1, %x3
|
||||
jmp outerloop
|
||||
swap:
|
||||
load %x3, $a, %x5
|
||||
load %x4, $a, %x6
|
||||
blt %x5, %x6, exchange
|
||||
addi %x4, 1, %x4
|
||||
jmp innerloopz
|
||||
exchange:
|
||||
sub %x7, %x7, %x7
|
||||
add %x0, %x5, %x7
|
||||
store %x6, 0, %x3
|
||||
store %x7, 0, %x4
|
||||
addi %x4, 1, %x4
|
||||
jmp innerloopz
|
File diff suppressed because it is too large
Load Diff
|
@ -1 +0,0 @@
|
|||
Hash of the Processor State = 255541867
|
Binary file not shown.
|
@ -1,15 +0,0 @@
|
|||
.data
|
||||
n:
|
||||
11
|
||||
.text
|
||||
main:
|
||||
load %x0, $n, %x3
|
||||
divi %x3, 2, %x3
|
||||
beq %x0, %x31, even
|
||||
sub %x10, %x10, %x10
|
||||
addi %x10, 1, %x10
|
||||
end
|
||||
even:
|
||||
sub %x10, $x10, %x10
|
||||
subi %x10, 1, %x10
|
||||
end
|
File diff suppressed because it is too large
Load Diff
|
@ -1 +0,0 @@
|
|||
Hash of the Processor State = -224294686
|
Binary file not shown.
|
@ -1,28 +0,0 @@
|
|||
.data
|
||||
n:
|
||||
10
|
||||
.text
|
||||
main:
|
||||
addi %x0, 0, %x3
|
||||
addi %x0, 1, %x4
|
||||
add %x3, %x4, %x5
|
||||
load %x0, $n, %x6
|
||||
addi %x0, 65535, %x7
|
||||
addi %x0, 0, %x8
|
||||
store %x3, 0, %x7
|
||||
subi %x7, 1, %x7
|
||||
addi %x8, 1, %x8
|
||||
store %x4, 0, %x7
|
||||
subi %x7, 1, %x7
|
||||
addi %x8, 1, %x8
|
||||
for:
|
||||
blt %x8, %x6, loop
|
||||
end
|
||||
loop:
|
||||
add %x3, %x4, %x5
|
||||
store %x5, 0, %x7
|
||||
subi %x7, 1, %x7
|
||||
addi %x8, 1, %x8
|
||||
add %x0, %x4, %x3
|
||||
add %x0, %x5, %x4
|
||||
jmp for
|
File diff suppressed because it is too large
Load Diff
|
@ -1 +0,0 @@
|
|||
Hash of the Processor State = -1518357572
|
Binary file not shown.
|
@ -1,23 +0,0 @@
|
|||
.data
|
||||
a:
|
||||
4567654
|
||||
.text
|
||||
main:
|
||||
load %x0, $a, %x3
|
||||
sub %x7, %x7, %x7
|
||||
loop:
|
||||
divi %x3, 10, %x4
|
||||
addi %x31, 0, %x30
|
||||
muli %x7, 10, %x7
|
||||
add %x7, %x30, %x7
|
||||
divi %x3, 10, %x3
|
||||
bgt %x3, %x0, loop
|
||||
load %x0, $a, %x5
|
||||
beq %x5, %x7, palindrome
|
||||
sub %x10, %x10, %x10
|
||||
subi %x10, 1, %x10
|
||||
end
|
||||
palindrome:
|
||||
sub %x10, %x10, %x10
|
||||
addi %x10, 1, %x10
|
||||
end
|
File diff suppressed because it is too large
Load Diff
|
@ -1,2 +0,0 @@
|
|||
Hash of the Processor State = 155317940
|
||||
|
Binary file not shown.
|
@ -1,24 +0,0 @@
|
|||
.data
|
||||
a:
|
||||
11
|
||||
.text
|
||||
main:
|
||||
load %x0, $a, %x3
|
||||
sub %x4, %x4, %x4
|
||||
divi %x3, 2, %x4
|
||||
sub %x6, %x6, %x6
|
||||
addi %x6, 2, %x6
|
||||
for:
|
||||
bgt %x6, %x4, prime
|
||||
div %x3, %x6, %x7
|
||||
beq %x0, %x31, notprime
|
||||
addi %x6, 1, %x6
|
||||
jmp for
|
||||
prime:
|
||||
sub %x10, %x10, %x10
|
||||
addi %x10, 1, %x10
|
||||
end
|
||||
notprime:
|
||||
sub %x10, %x10, %x10
|
||||
subi %x10, 1, %x10
|
||||
end
|
File diff suppressed because it is too large
Load Diff
|
@ -1 +0,0 @@
|
|||
Hash of the Processor State = -1414219998
|
Binary file not shown.
|
@ -1,92 +0,0 @@
|
|||
#!/bin/python
|
||||
|
||||
import sys
|
||||
import os
|
||||
import zipfile
|
||||
import shutil
|
||||
import subprocess
|
||||
from threading import Timer
|
||||
|
||||
zip_file = sys.argv[1]
|
||||
|
||||
l = len(zip_file.split("/"))
|
||||
print "Students :"
|
||||
for i in range(0, len(zip_file.split("/")[l-1].split("_"))):
|
||||
print zip_file.split("/")[l-1].split("_")[i].split(".")[0]
|
||||
print ""
|
||||
|
||||
submissions_temp_dir = "./submissions/"
|
||||
|
||||
if not os.path.exists(submissions_temp_dir):
|
||||
os.mkdir(submissions_temp_dir)
|
||||
|
||||
zip_ref = zipfile.ZipFile(zip_file, 'r')
|
||||
zip_ref.extractall(submissions_temp_dir)
|
||||
zip_ref.close()
|
||||
|
||||
shutil.copyfile("build.xml", submissions_temp_dir + "/build.xml")
|
||||
|
||||
os.chdir(submissions_temp_dir)
|
||||
|
||||
stdout_file = open("./tmp.output", 'a')
|
||||
popen_args = ["ant", "make-jar"]
|
||||
proc = subprocess.Popen(popen_args, stdout = stdout_file, stderr = stdout_file)
|
||||
timer = Timer(5, proc.kill)
|
||||
try:
|
||||
timer.start()
|
||||
stdout, stderr = proc.communicate()
|
||||
finally:
|
||||
timer.cancel()
|
||||
stdout_file.close()
|
||||
|
||||
if not os.path.exists("jars/simulator.jar"):
|
||||
print "compilation failed. jar file not created"
|
||||
sys.exit(0)
|
||||
|
||||
test_cases_dir = "../test_cases"
|
||||
total_marks = 0
|
||||
scored_marks = 0
|
||||
for testcase in os.listdir(test_cases_dir):
|
||||
if ".out" in testcase:
|
||||
total_marks = total_marks + 1
|
||||
|
||||
stdout_file = open("./" + testcase.split(".")[0] + ".observedoutput", 'w')
|
||||
popen_args = ["java", "-Xmx1g", "-jar", "jars/simulator.jar", "./src/configuration/config.xml", "./" + testcase.split(".")[0] + ".observedstat", test_cases_dir + "/" + testcase]
|
||||
# print popen_args
|
||||
proc = subprocess.Popen(popen_args, stdout = stdout_file, stderr = stdout_file)
|
||||
timer = Timer(5, proc.kill)
|
||||
try:
|
||||
timer.start()
|
||||
stdout, stderr = proc.communicate()
|
||||
finally:
|
||||
timer.cancel()
|
||||
stdout_file.close()
|
||||
|
||||
if os.path.exists("./" + testcase.split(".")[0] + ".observedoutput"):
|
||||
expectedoutput_file = open(test_cases_dir + "/" + testcase.split(".")[0] + ".expected")
|
||||
expected_hash = expectedoutput_file.readline()
|
||||
expectedoutput_file.close()
|
||||
|
||||
correct = False
|
||||
observedoutput_file = open("./" + testcase.split(".")[0] + ".observedoutput")
|
||||
for line in observedoutput_file:
|
||||
# if "Hash" in line:
|
||||
# print "computed = " + line
|
||||
# print "expected = " + expected_hash
|
||||
if line == expected_hash:
|
||||
correct = True
|
||||
break
|
||||
observedoutput_file.close()
|
||||
if correct == True:
|
||||
scored_marks = scored_marks + 1
|
||||
print testcase + " : PASS!"
|
||||
else:
|
||||
print testcase + " : fail - incorrect hash"
|
||||
else:
|
||||
print testcase + " : fail - standard output file not created"
|
||||
|
||||
os.chdir("..")
|
||||
|
||||
shutil.rmtree(submissions_temp_dir)
|
||||
|
||||
print "\ntotal score = " + str(scored_marks) + " out of " + str(total_marks)
|
Loading…
Reference in New Issue