200010030
/
coa-lab
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

added report

This commit is contained in:
karthikmurakonda 2022-11-09 10:38:46 +05:30
parent 2fd9d08680
commit a97b8f3feb
5 changed files with 53 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
assignment-6/bin/configuration/config.xml Normal file
View File

@ -0,0 +1,43 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Configuration>
<FunctionalUnits>
<ALU>
<Count>2</Count>
<Latency>1</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</ALU>
<Multiplier>
<Count>1</Count>
<Latency>4</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</Multiplier>
<Divider>
<Count>1</Count>
<Latency>10</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</Divider>
</FunctionalUnits>
<L1iCache>
<NumberOfLines>256</NumberOfLines>
<Latency>2</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L1iCache>
<L1dCache>
<NumberOfLines>256</NumberOfLines>
<Latency>2</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L1dCache>
<L2Cache>
<NumberOfLines>2048</NumberOfLines>
<Latency>10</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L2Cache>
<MainMemoryLatency>40</MainMemoryLatency>
</Configuration>

4
assignment-6/bin/hello.txt Normal file
View File

@ -0,0 +1,4 @@
Number of instructions executed = 340
Number of cycles taken = 15080
Number of data hazards = 373
Number of control hazards = 166

BIN
assignment-6/report.pdf Normal file
View File

Binary file not shown.

8
assignment-6/src/hello.txt
View File

@ -1,4 +1,4 @@
Number of instructions executed = 5 Number of instructions executed = 365
Number of cycles taken = 224 Number of cycles taken = 15815
Number of data hazards = 5 Number of data hazards = 393
Number of control hazards = 0 Number of control hazards = 176

4
assignment-6/src/processor/Processor.java
View File

@ -47,8 +47,8 @@ public class Processor {
EX_IF_Latch = new EX_IF_LatchType(); EX_IF_Latch = new EX_IF_LatchType();
MA_RW_Latch = new MA_RW_LatchType(); MA_RW_Latch = new MA_RW_LatchType();
l1iCache = new Cache(this, 1, 16); l1iCache = new Cache(this, 0, 16);
l1dCache = new Cache(this, 4, 1024); l1dCache = new Cache(this, 0, 16);
IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch); IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch);
OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch); OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch);