intermediate commit
Co-authored-by: SriRam Mudragada <iam-msr@users.noreply.github.com>
This commit is contained in:
karthikmurakonda
parent
f242de6bc8
commit
2fd9d08680
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@ -0,0 +1,18 @@
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.data
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n:x5x5x5
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59
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.text
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main:
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load %x0, $n, %x3
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addi %x4, 2, %x4
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forloop:
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div %x3, %x4, %x6
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beq %x31, %x7, nonprime
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addi %x4, 1, %x4
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blt %x4, %x3, forloop
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prime:
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addi %x5, 1, %x5
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end
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nonprime:
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subi %x5, 1, %x5
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end
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@ -0,0 +1 @@
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Subproject commit f483ee2c38c1a35be3533c9433f7375235295d10
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Binary file not shown.
Binary file not shown.
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@ -1,39 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<!-- WARNING: Eclipse auto-generated file.
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Any modifications will be overwritten.
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To include a user specific buildfile here, simply create one in the same
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directory with the processing instruction <?eclipse.ant.import?>
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as the first entry and export the buildfile again. --><project basedir="." default="build">
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<property environment="env"/>
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<property name="debuglevel" value="source,lines,vars"/>
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<property name="target" value="1.8"/>
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<property name="source" value="1.8"/>
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<target name="init">
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<mkdir dir="bin"/>
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<copy includeemptydirs="false" todir="bin">
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<fileset dir="src">
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<exclude name="**/*.launch"/>
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<exclude name="**/*.java"/>
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</fileset>
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</copy>
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</target>
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<target name="clean">
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<delete dir="bin"/>
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</target>
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<target depends="clean" name="cleanall"/>
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<target depends="build-subprojects,build-project" name="build"/>
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<target name="build-subprojects"/>
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<target depends="init" name="build-project">
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<javac debug="true" debuglevel="${debuglevel}" destdir="bin" includeantruntime="false" source="${source}" target="${target}">
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<src path="src"/>
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</javac>
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</target>
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<target name="make-jar" depends="build">
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<mkdir dir="jars"/>
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<jar destfile="jars/simulator.jar" basedir="bin">
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<manifest>
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<attribute name="Main-Class" value="main.Main"/>
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</manifest>
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</jar>
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</target>
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</project>
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@ -1,43 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Configuration>
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<FunctionalUnits>
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<ALU>
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<Count>2</Count>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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</ALU>
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<Multiplier>
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<Count>1</Count>
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<Latency>4</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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</Multiplier>
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<Divider>
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<Count>1</Count>
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<Latency>10</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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</Divider>
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</FunctionalUnits>
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<L1iCache>
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<NumberOfLines>256</NumberOfLines>
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<Latency>2</Latency>
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<Associativity>4</Associativity>
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<ReplacementPolicy>LRU</ReplacementPolicy>
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</L1iCache>
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<L1dCache>
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<NumberOfLines>256</NumberOfLines>
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<Latency>2</Latency>
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<Associativity>4</Associativity>
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<ReplacementPolicy>LRU</ReplacementPolicy>
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</L1dCache>
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<L2Cache>
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<NumberOfLines>2048</NumberOfLines>
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<Latency>10</Latency>
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<Associativity>4</Associativity>
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<ReplacementPolicy>LRU</ReplacementPolicy>
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</L2Cache>
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<MainMemoryLatency>40</MainMemoryLatency>
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</Configuration>
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@ -1,4 +0,0 @@
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Number of instructions executed = 6
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Number of cycles taken = 252
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Number of data hazards = 7
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Number of control hazards = 0
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Binary file not shown.
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@ -1,4 +1,4 @@
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Number of instructions executed = 263
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Number of cycles taken = 13761
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Number of data hazards = 203
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Number of control hazards = 164
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Number of instructions executed = 5
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Number of cycles taken = 224
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Number of data hazards = 5
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Number of control hazards = 0
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@ -1,5 +1,6 @@
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package processor;
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import processor.memorysystem.Cache;
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import processor.memorysystem.MainMemory;
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import processor.pipeline.EX_IF_LatchType;
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import processor.pipeline.EX_MA_LatchType;
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@ -31,6 +32,8 @@ public class Processor {
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Execute EXUnit;
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MemoryAccess MAUnit;
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RegisterWrite RWUnit;
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Cache l1iCache;
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Cache l1dCache;
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public Processor()
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{
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@ -43,6 +46,9 @@ public class Processor {
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EX_MA_Latch = new EX_MA_LatchType();
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EX_IF_Latch = new EX_IF_LatchType();
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MA_RW_Latch = new MA_RW_LatchType();
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l1iCache = new Cache(this, 1, 16);
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l1dCache = new Cache(this, 4, 1024);
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IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch);
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OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch);
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@ -94,4 +100,12 @@ public class Processor {
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return RWUnit;
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}
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public Cache getL1iCache() {
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return l1iCache;
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}
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public Cache getL1dCache() {
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return l1dCache;
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}
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}
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@ -0,0 +1,119 @@
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package processor.memorysystem;
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import generic.*;
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import processor.*;
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import configuration.Configuration;
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public class Cache implements Element {
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boolean isPresent = true;
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public int latency;
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Processor containingProcessor;
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int cache_size, miss_addr, line_size;
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CacheLine[] cach;
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int[] index;
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public Cache(Processor containingProcessor, int latency, int cacheSize) {
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this.latency = latency;
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this.cache_size = cacheSize;
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this.line_size = (int) (Math.log(this.cache_size / 8) / Math.log(2));
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this.containingProcessor = containingProcessor;
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this.cach = new CacheLine[cache_size / 8];
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for (int i = 0; i < cache_size / 8; i++)
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this.cach[i] = new CacheLine();
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}
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private int[] getindextag(int addr){
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String a = Integer.toBinaryString(addr);
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for (int i = 0; i < 32 - a.length(); i++)
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a = "0" + a;
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int add_tag = Integer.parseInt(a.substring(0, a.length() - line_size), 2);
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int temp_ind;
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String ind = "0";
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if (line_size == 0)
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temp_ind = 0;
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else
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for (int i = 0; i < line_size; i++)
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ind = ind + "1";
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temp_ind = addr & Integer.parseInt(ind, 2);
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return new int[]{temp_ind, add_tag};
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}
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public int cacheRead(int address) {
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int index, tag;
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int[] temp = getindextag(address);
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index = temp[0];
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tag = temp[1];
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if (tag == cach[index].tag[0]) {
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cach[index].least_recently_used = 1;
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isPresent = true;
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return cach[index].data[0];
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} else if (tag == cach[index].tag[1]) {
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cach[index].least_recently_used = 0;
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isPresent = true;
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return cach[index].data[1];
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} else {
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isPresent = false;
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return -1;
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}
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}
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public void WritetoCache(int address, int value) {
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int index, tag;
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int[] temp = getindextag(address);
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index = temp[0];
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tag = temp[1];
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cach[index].setValue(tag, value);
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}
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@Override
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public void handleEvent(Event source_event) {
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if (source_event.getEventType() == Event.EventType.MemoryRead) {
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System.out.println("handle event cache memory read");
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MemoryReadEvent handle_event = (MemoryReadEvent) source_event;
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int data = cacheRead(handle_event.getAddressToReadFrom());
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if (isPresent == true) {
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Simulator.getEventQueue().addEvent(
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new MemoryResponseEvent(
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Clock.getCurrentTime() + this.latency,
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this,
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handle_event.getRequestingElement(),
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data));
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} else {
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handle_event.setEventTime(Clock.getCurrentTime() + Configuration.mainMemoryLatency + 1);
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this.miss_addr = handle_event.getAddressToReadFrom();
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Simulator.getEventQueue().addEvent(handle_event);
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Simulator.getEventQueue().addEvent(
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new MemoryReadEvent(
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Clock.getCurrentTime() + Configuration.mainMemoryLatency,
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this,
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containingProcessor.getMainMemory(),
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this.miss_addr)
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);
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}
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}
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else if (source_event.getEventType() == Event.EventType.MemoryWrite) {
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MemoryWriteEvent handle_event = (MemoryWriteEvent) source_event;
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WritetoCache(handle_event.getAddressToWriteTo(), handle_event.getValue());
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containingProcessor.getMainMemory().setWord(handle_event.getAddressToWriteTo(), handle_event.getValue());
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Simulator.getEventQueue().addEvent(
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new ExecutionCompleteEvent(
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Clock.getCurrentTime() + Configuration.mainMemoryLatency,
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containingProcessor.getMainMemory(),
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handle_event.getRequestingElement()));
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}
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else if (source_event.getEventType() == Event.EventType.MemoryResponse) {
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MemoryResponseEvent handle_event = (MemoryResponseEvent) source_event;
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WritetoCache(this.miss_addr, handle_event.getValue());
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}
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}
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}
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package processor.memorysystem;
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public class CacheLine{
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int[] tag = new int[2];
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int[] data = new int[2];
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int least_recently_used = 0;
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public CacheLine() {
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this.tag[0] = -1;
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this.tag[1] = -1;
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}
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public void setValue(int tag, int value) {
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if(tag == this.tag[0]) {
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this.data[0] = value;
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this.least_recently_used = 1;
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}
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else if(tag == this.tag[1]) {
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this.data[1] = value;
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this.least_recently_used = 0;
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}
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else {
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this.tag[this.least_recently_used] = tag;
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this.data[this.least_recently_used] = value;
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this.least_recently_used = 1- this.least_recently_used;
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}
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}
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}
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@ -1,6 +1,5 @@
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package processor.pipeline;
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import configuration.Configuration;
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import generic.Element;
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import generic.Event;
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import generic.MemoryReadEvent;
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@ -33,13 +32,13 @@ public class InstructionFetch implements Element{
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Simulator.getEventQueue().addEvent(
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new MemoryReadEvent(
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Clock.getCurrentTime()+Configuration.mainMemoryLatency,
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Clock.getCurrentTime() + containingProcessor.getL1iCache().latency,
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this,
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containingProcessor.getMainMemory(),
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containingProcessor.getL1iCache(),
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currentPC
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)
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);
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System.out.println("H1");
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// System.out.println("H1");
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IF_OF_Latch.setIF_branching_busy(true);
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@ -58,9 +57,9 @@ public class InstructionFetch implements Element{
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Simulator.getEventQueue().addEvent(
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new MemoryReadEvent(
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Clock.getCurrentTime()+ Configuration.mainMemoryLatency,
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Clock.getCurrentTime()+ containingProcessor.getL1iCache().latency,
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this,
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containingProcessor.getMainMemory(),
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containingProcessor.getL1iCache(),
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currentPC
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)
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);
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@ -1,6 +1,5 @@
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package processor.pipeline;
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import configuration.Configuration;
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import generic.Element;
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import generic.Event;
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import generic.ExecutionCompleteEvent;
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@ -41,9 +40,9 @@ public class MemoryAccess implements Element {
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instruction.getSourceOperand1().getValue());
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Simulator.getEventQueue().addEvent(
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new MemoryWriteEvent(
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Clock.getCurrentTime()+Configuration.mainMemoryLatency,
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Clock.getCurrentTime()+containingProcessor.getL1dCache().latency,
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this,
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containingProcessor.getMainMemory(),
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containingProcessor.getL1dCache(),
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alu_result,
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val_store
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)
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@ -55,9 +54,9 @@ public class MemoryAccess implements Element {
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{
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Simulator.getEventQueue().addEvent(
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new MemoryReadEvent(
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Clock.getCurrentTime()+Configuration.mainMemoryLatency,
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Clock.getCurrentTime()+containingProcessor.getL1dCache().latency,
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this,
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containingProcessor.getMainMemory(),
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containingProcessor.getL1dCache(),
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alu_result
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)
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);
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