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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Configuration>
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	<FunctionalUnits>
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		<ALU>
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			<Count>2</Count>
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			<Latency>1</Latency>
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			<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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		</ALU>
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		<Multiplier>
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			<Count>1</Count>
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			<Latency>4</Latency>
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			<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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		</Multiplier>
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		<Divider>
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			<Count>1</Count>
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			<Latency>10</Latency>
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			<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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		</Divider>
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	</FunctionalUnits>
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	<L1iCache>
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		<NumberOfLines>256</NumberOfLines>
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		<Latency>2</Latency>
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		<Associativity>4</Associativity>
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		<ReplacementPolicy>LRU</ReplacementPolicy>
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	</L1iCache>
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	<L1dCache>
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		<NumberOfLines>256</NumberOfLines>
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		<Latency>2</Latency>
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		<Associativity>4</Associativity>
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		<ReplacementPolicy>LRU</ReplacementPolicy>
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	</L1dCache>
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	<L2Cache>
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		<NumberOfLines>2048</NumberOfLines>
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		<Latency>10</Latency>
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		<Associativity>4</Associativity>
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		<ReplacementPolicy>LRU</ReplacementPolicy>
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	</L2Cache>
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	<MainMemoryLatency>40</MainMemoryLatency>
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</Configuration>
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Number of instructions executed = 340
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Number of cycles taken = 15080
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Number of data hazards = 373
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Number of control hazards = 166
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			@ -1,4 +1,4 @@
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Number of instructions executed = 5
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Number of cycles taken = 224
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Number of data hazards = 5
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Number of control hazards = 0
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Number of instructions executed = 365
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Number of cycles taken = 15815
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Number of data hazards = 393
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Number of control hazards = 176
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			@ -47,8 +47,8 @@ public class Processor {
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		EX_IF_Latch = new EX_IF_LatchType();
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		MA_RW_Latch = new MA_RW_LatchType();
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		l1iCache = new Cache(this, 1, 16);
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		l1dCache = new Cache(this, 4, 1024);
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		l1iCache = new Cache(this, 0, 16);
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		l1dCache = new Cache(this, 0, 16);
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		IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch);
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		OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch);
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