intermediate commit

Co-authored-by: SriRam Mudragada <iam-msr@users.noreply.github.com>
This commit is contained in:
karthikmurakonda 2022-11-04 23:42:36 +05:30
parent f242de6bc8
commit 2fd9d08680
14 changed files with 195 additions and 101 deletions

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@ -0,0 +1,18 @@
.data
n:x5x5x5
59
.text
main:
load %x0, $n, %x3
addi %x4, 2, %x4
forloop:
div %x3, %x4, %x6
beq %x31, %x7, nonprime
addi %x4, 1, %x4
blt %x4, %x3, forloop
prime:
addi %x5, 1, %x5
end
nonprime:
subi %x5, 1, %x5
end

@ -0,0 +1 @@
Subproject commit f483ee2c38c1a35be3533c9433f7375235295d10

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@ -1,39 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- WARNING: Eclipse auto-generated file.
Any modifications will be overwritten.
To include a user specific buildfile here, simply create one in the same
directory with the processing instruction <?eclipse.ant.import?>
as the first entry and export the buildfile again. --><project basedir="." default="build">
<property environment="env"/>
<property name="debuglevel" value="source,lines,vars"/>
<property name="target" value="1.8"/>
<property name="source" value="1.8"/>
<target name="init">
<mkdir dir="bin"/>
<copy includeemptydirs="false" todir="bin">
<fileset dir="src">
<exclude name="**/*.launch"/>
<exclude name="**/*.java"/>
</fileset>
</copy>
</target>
<target name="clean">
<delete dir="bin"/>
</target>
<target depends="clean" name="cleanall"/>
<target depends="build-subprojects,build-project" name="build"/>
<target name="build-subprojects"/>
<target depends="init" name="build-project">
<javac debug="true" debuglevel="${debuglevel}" destdir="bin" includeantruntime="false" source="${source}" target="${target}">
<src path="src"/>
</javac>
</target>
<target name="make-jar" depends="build">
<mkdir dir="jars"/>
<jar destfile="jars/simulator.jar" basedir="bin">
<manifest>
<attribute name="Main-Class" value="main.Main"/>
</manifest>
</jar>
</target>
</project>

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@ -1,43 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Configuration>
<FunctionalUnits>
<ALU>
<Count>2</Count>
<Latency>1</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</ALU>
<Multiplier>
<Count>1</Count>
<Latency>4</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</Multiplier>
<Divider>
<Count>1</Count>
<Latency>10</Latency>
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
</Divider>
</FunctionalUnits>
<L1iCache>
<NumberOfLines>256</NumberOfLines>
<Latency>2</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L1iCache>
<L1dCache>
<NumberOfLines>256</NumberOfLines>
<Latency>2</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L1dCache>
<L2Cache>
<NumberOfLines>2048</NumberOfLines>
<Latency>10</Latency>
<Associativity>4</Associativity>
<ReplacementPolicy>LRU</ReplacementPolicy>
</L2Cache>
<MainMemoryLatency>40</MainMemoryLatency>
</Configuration>

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@ -1,4 +0,0 @@
Number of instructions executed = 6
Number of cycles taken = 252
Number of data hazards = 7
Number of control hazards = 0

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@ -1,4 +1,4 @@
Number of instructions executed = 263
Number of cycles taken = 13761
Number of data hazards = 203
Number of control hazards = 164
Number of instructions executed = 5
Number of cycles taken = 224
Number of data hazards = 5
Number of control hazards = 0

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@ -1,5 +1,6 @@
package processor;
import processor.memorysystem.Cache;
import processor.memorysystem.MainMemory;
import processor.pipeline.EX_IF_LatchType;
import processor.pipeline.EX_MA_LatchType;
@ -31,6 +32,8 @@ public class Processor {
Execute EXUnit;
MemoryAccess MAUnit;
RegisterWrite RWUnit;
Cache l1iCache;
Cache l1dCache;
public Processor()
{
@ -43,6 +46,9 @@ public class Processor {
EX_MA_Latch = new EX_MA_LatchType();
EX_IF_Latch = new EX_IF_LatchType();
MA_RW_Latch = new MA_RW_LatchType();
l1iCache = new Cache(this, 1, 16);
l1dCache = new Cache(this, 4, 1024);
IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch);
OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch);
@ -94,4 +100,12 @@ public class Processor {
return RWUnit;
}
public Cache getL1iCache() {
return l1iCache;
}
public Cache getL1dCache() {
return l1dCache;
}
}

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@ -0,0 +1,119 @@
package processor.memorysystem;
import generic.*;
import processor.*;
import configuration.Configuration;
public class Cache implements Element {
boolean isPresent = true;
public int latency;
Processor containingProcessor;
int cache_size, miss_addr, line_size;
CacheLine[] cach;
int[] index;
public Cache(Processor containingProcessor, int latency, int cacheSize) {
this.latency = latency;
this.cache_size = cacheSize;
this.line_size = (int) (Math.log(this.cache_size / 8) / Math.log(2));
this.containingProcessor = containingProcessor;
this.cach = new CacheLine[cache_size / 8];
for (int i = 0; i < cache_size / 8; i++)
this.cach[i] = new CacheLine();
}
private int[] getindextag(int addr){
String a = Integer.toBinaryString(addr);
for (int i = 0; i < 32 - a.length(); i++)
a = "0" + a;
int add_tag = Integer.parseInt(a.substring(0, a.length() - line_size), 2);
int temp_ind;
String ind = "0";
if (line_size == 0)
temp_ind = 0;
else
for (int i = 0; i < line_size; i++)
ind = ind + "1";
temp_ind = addr & Integer.parseInt(ind, 2);
return new int[]{temp_ind, add_tag};
}
public int cacheRead(int address) {
int index, tag;
int[] temp = getindextag(address);
index = temp[0];
tag = temp[1];
if (tag == cach[index].tag[0]) {
cach[index].least_recently_used = 1;
isPresent = true;
return cach[index].data[0];
} else if (tag == cach[index].tag[1]) {
cach[index].least_recently_used = 0;
isPresent = true;
return cach[index].data[1];
} else {
isPresent = false;
return -1;
}
}
public void WritetoCache(int address, int value) {
int index, tag;
int[] temp = getindextag(address);
index = temp[0];
tag = temp[1];
cach[index].setValue(tag, value);
}
@Override
public void handleEvent(Event source_event) {
if (source_event.getEventType() == Event.EventType.MemoryRead) {
System.out.println("handle event cache memory read");
MemoryReadEvent handle_event = (MemoryReadEvent) source_event;
int data = cacheRead(handle_event.getAddressToReadFrom());
if (isPresent == true) {
Simulator.getEventQueue().addEvent(
new MemoryResponseEvent(
Clock.getCurrentTime() + this.latency,
this,
handle_event.getRequestingElement(),
data));
} else {
handle_event.setEventTime(Clock.getCurrentTime() + Configuration.mainMemoryLatency + 1);
this.miss_addr = handle_event.getAddressToReadFrom();
Simulator.getEventQueue().addEvent(handle_event);
Simulator.getEventQueue().addEvent(
new MemoryReadEvent(
Clock.getCurrentTime() + Configuration.mainMemoryLatency,
this,
containingProcessor.getMainMemory(),
this.miss_addr)
);
}
}
else if (source_event.getEventType() == Event.EventType.MemoryWrite) {
MemoryWriteEvent handle_event = (MemoryWriteEvent) source_event;
WritetoCache(handle_event.getAddressToWriteTo(), handle_event.getValue());
containingProcessor.getMainMemory().setWord(handle_event.getAddressToWriteTo(), handle_event.getValue());
Simulator.getEventQueue().addEvent(
new ExecutionCompleteEvent(
Clock.getCurrentTime() + Configuration.mainMemoryLatency,
containingProcessor.getMainMemory(),
handle_event.getRequestingElement()));
}
else if (source_event.getEventType() == Event.EventType.MemoryResponse) {
MemoryResponseEvent handle_event = (MemoryResponseEvent) source_event;
WritetoCache(this.miss_addr, handle_event.getValue());
}
}
}

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@ -0,0 +1,30 @@
package processor.memorysystem;
public class CacheLine{
int[] tag = new int[2];
int[] data = new int[2];
int least_recently_used = 0;
public CacheLine() {
this.tag[0] = -1;
this.tag[1] = -1;
}
public void setValue(int tag, int value) {
if(tag == this.tag[0]) {
this.data[0] = value;
this.least_recently_used = 1;
}
else if(tag == this.tag[1]) {
this.data[1] = value;
this.least_recently_used = 0;
}
else {
this.tag[this.least_recently_used] = tag;
this.data[this.least_recently_used] = value;
this.least_recently_used = 1- this.least_recently_used;
}
}
}

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@ -1,6 +1,5 @@
package processor.pipeline;
import configuration.Configuration;
import generic.Element;
import generic.Event;
import generic.MemoryReadEvent;
@ -33,13 +32,13 @@ public class InstructionFetch implements Element{
Simulator.getEventQueue().addEvent(
new MemoryReadEvent(
Clock.getCurrentTime()+Configuration.mainMemoryLatency,
Clock.getCurrentTime() + containingProcessor.getL1iCache().latency,
this,
containingProcessor.getMainMemory(),
containingProcessor.getL1iCache(),
currentPC
)
);
System.out.println("H1");
// System.out.println("H1");
IF_OF_Latch.setIF_branching_busy(true);
@ -58,9 +57,9 @@ public class InstructionFetch implements Element{
Simulator.getEventQueue().addEvent(
new MemoryReadEvent(
Clock.getCurrentTime()+ Configuration.mainMemoryLatency,
Clock.getCurrentTime()+ containingProcessor.getL1iCache().latency,
this,
containingProcessor.getMainMemory(),
containingProcessor.getL1iCache(),
currentPC
)
);

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@ -1,6 +1,5 @@
package processor.pipeline;
import configuration.Configuration;
import generic.Element;
import generic.Event;
import generic.ExecutionCompleteEvent;
@ -41,9 +40,9 @@ public class MemoryAccess implements Element {
instruction.getSourceOperand1().getValue());
Simulator.getEventQueue().addEvent(
new MemoryWriteEvent(
Clock.getCurrentTime()+Configuration.mainMemoryLatency,
Clock.getCurrentTime()+containingProcessor.getL1dCache().latency,
this,
containingProcessor.getMainMemory(),
containingProcessor.getL1dCache(),
alu_result,
val_store
)
@ -55,9 +54,9 @@ public class MemoryAccess implements Element {
{
Simulator.getEventQueue().addEvent(
new MemoryReadEvent(
Clock.getCurrentTime()+Configuration.mainMemoryLatency,
Clock.getCurrentTime()+containingProcessor.getL1dCache().latency,
this,
containingProcessor.getMainMemory(),
containingProcessor.getL1dCache(),
alu_result
)
);