939 lines
44 KiB
XML
Executable File
939 lines
44 KiB
XML
Executable File
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!--/*****************************************************************************
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Tejas Simulator
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*************************************************************************************
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Copyright 2010 Indian Institute of Technology, Delhi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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******************************************************************************
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Contributors: Moksh Upadhyay, Abhishek Sagar, Prathmesh Kallurkar
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*****************************************************************************
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based on Intel® Core™ i5-7200U (Kabylake) Processor
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https://en.wikichip.org/wiki/intel/core_i5/i5-7200u
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https://www.agner.org/optimize/instruction_tables.pdf
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TDP = 15W
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42 mm * 24 mm
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/-->
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<Configuration>
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<Emulator>
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<!--Emulator type and communication type define what is the input for instruction data to Tejas-->
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<!--Currently we support following (emulator,communication) combinations : -->
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<!--(pin, sharedMemory), (qemu, sharedMemory), (qemu, network), (none, file)-->
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<!--(pin,file) combination can be used to collect execution trace of an application in a compressed file-->
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<EmulatorType>none</EmulatorType> <!--pin,qemu-->
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<!--NOTE only file interface supports the execution of multiple benchmarks inside tejas-->
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<!--if you are reading the packets from a file, the emulator must be set to none-->
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<!--multiple benchmarks are specified using arguments to the simulator-->
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<CommunicationType>file</CommunicationType> <!--file,sharedMemory,network-->
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<isVISATrace>false</isVISATrace> <!-- If communication type is file, is it a VISA trace? -->
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<!--We can use tejas as an interface to create a compressed (gzip) trace file using the emulator-->
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<!--Set this option to true if you want to create a trace file of the benchmark execution-->
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<!--In this mode, Tejas will be used only as an interface to the emulator. NO simulation will be performed-->
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<!--Right now, this option is valid ONLY for emulator type pin and communication type file-->
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<StoreExecutionTraceInAFile>false</StoreExecutionTraceInAFile>
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<!-- If store packets in a file option is set to true, this parameter indicates the basename for the trace files -->
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<!--One trace file is maintained for each store. The name of trace file for core n is basename_n.gz-->
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<!--We do not allow overwriting of trace files. So if a tracefile with same name is pre-existing, kindly rename it-->
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<BasenameForTraceFiles>/home/rajshekar/projects/tejas/tests/test1_trace</BasenameForTraceFiles>
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<PinTool>/mnt/remote_scratch/softwares/pin-97554/</PinTool>
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<PinInstrumentor>/mnt/remote_scratch1/rajshekar/projects/tejas/workspace/Tejas/src/emulator/pin/obj-pin/causalityTool.so</PinInstrumentor>
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<QemuTool>TODO/home/prathmesh/workspace/qemu/x86_64-linux-user/qemu-x86_64 /home/prathmesh/tmp/testQemu.o</QemuTool>
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<ShmLibDirectory>/mnt/remote_scratch1/rajshekar/projects/tejas/workspace/Tejas/src/emulator/pin/obj-comm/</ShmLibDirectory>
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<GetBenchmarkPIDScript>/home/rajshekar/resources/tejas_configs/getBenchmarkPID.sh</GetBenchmarkPIDScript>
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<KillEmulatorScript>/home/rajshekar/resources/tejas_configs/killAllDescendents.sh</KillEmulatorScript>
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</Emulator>
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<!--Simulation Parameters-->
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<Simulation>
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<CollectInsnWorkingSet>false</CollectInsnWorkingSet>
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<InsnWorkingSetChunkSize>3000000</InsnWorkingSetChunkSize> <!--Chunk size of instructions over which working set must be noted-->
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<CollectDataWorkingSet>false</CollectDataWorkingSet>
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<DataWorkingSetChunkSize>3000000</DataWorkingSetChunkSize> <!--Chunk size of instructions over which working set must be noted-->
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<NumTempIntReg>16</NumTempIntReg> <!--Number of temporary Integer registers-->
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<IndexAddrModeEnable>0</IndexAddrModeEnable> <!--Indexed addressing mode Enabled or disabled (Write 1 for YES, 0 for NO)-->
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<EmuCores>0</EmuCores> <!--The cores on which emulator will run(supports ',' and '-' for ranges)-->
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<JavaCores>1</JavaCores> <!--The cores on which simulator will run(supports ',' and '-' for ranges)-->
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<DebugMode>false</DebugMode> <!--True if debug related printing is desired-->
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<DetachMemSysData>false</DetachMemSysData>
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<DetachMemSysInsn>false</DetachMemSysInsn>
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<PrintPowerStats>true</PrintPowerStats>
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<Broadcast>false</Broadcast>
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<pinpointsSim>false</pinpointsSim>
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<pinpointsFile>/mnt/srishtistr0/scratch/rajshekar/tejas/PinPoints_working_directory/soplex.test.Data/t.sorted</pinpointsFile>
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<NumInsToIgnore>00000000</NumInsToIgnore> <!--Ignores these many profilable instructions from the start of the program-->
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<subsetSim>true</subsetSim>
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<subsetSimSize>2000000</subsetSimSize>
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<markerFunctions>false</markerFunctions>
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<startSimMarker>add</startSimMarker>
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<endSimMarker>sub</endSimMarker>
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<NumCores>2</NumCores>
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</Simulation>
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<Applications> <!-- Applications (traces) to run -->
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<Benchmark>
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<BenchmarkPath>/store/Documents/B_Tech/Semester_7/ACA/Tejas-Dh/traces/qemuTrace/7zip</BenchmarkPath> <!-- Path to the benchmark traces -->
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<Threads>2</Threads> <!-- Number of threads for the trace -->
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</Benchmark>
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</Applications>
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<!--System Parameters-->
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<System>
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<MainMemory>
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<MemControllerToUse>SIMPLE</MemControllerToUse> <!-- Set the value as DRAM to enable DRAM else use SIMPLE to disable DRAM -->
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<MainMemoryLatency>132</MainMemoryLatency> <!--The latency of main memory (in clock cycles)-->
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<MainMemoryFrequency>2400</MainMemoryFrequency> <!--Operating frequency of the main memory (in MHz)-->
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<MainMemoryPortType>FCFS</MainMemoryPortType> <!--Type of access ports in the Main Memory (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
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<MainMemoryAccessPorts>1</MainMemoryAccessPorts> <!--Number of access ports in the Main Memory-->
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<MainMemoryPortOccupancy>1</MainMemoryPortOccupancy> <!--The occupancy of the Main Memory ports (in clock cycles)-->
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<LeakageEnergy>0.0073</LeakageEnergy>
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<DynamicEnergy>0.0544</DynamicEnergy>
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</MainMemory>
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<CacheBusLatency>1</CacheBusLatency> <!--Latency of the RING used for broadcasting messages for cache coherence-->
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<GlobalClock>
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<LeakageEnergy>0.3456</LeakageEnergy>
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<DynamicEnergy>0.2886</DynamicEnergy>
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</GlobalClock>
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<!--Core Parameters-->
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<Core>
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<CoreNumber>0-1</CoreNumber>
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<CoreFrequency>2500</CoreFrequency> <!--Operating frequency of the core (in MHz)-->
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<PipelineType>outOfOrder</PipelineType> <!--inOrder,outOfOrder(set issue width for multi-issue in-order)-->
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<BranchPredictor>
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<Predictor_Mode>TAGE-SC-L</Predictor_Mode> <!-- Legal Values are NoPredictor, PerfectPredictor, AlwaysTaken, AlwaysNotTaken, Tournament, Bimodal, GAg, GAp, GShare, PAg, PAp, TAGE, TAGE-SC-L -->
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<PCBits>8</PCBits>
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<BHRsize>16</BHRsize>
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<BranchMispredPenalty>17</BranchMispredPenalty> <!--Branch misprediction penalty--><!-- https://www.7-cpu.com/cpu/Skylake.html -->
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<SaturatingBits>2</SaturatingBits>
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<TAGESCLLibDirectory>/mnt/remote_scratch1/rajshekar/projects/tejas/workspace/Tejas/src/simulator/pipeline/branchpredictor/TAGESCL/</TAGESCLLibDirectory>
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<LeakageEnergy>0.0178</LeakageEnergy>
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<DynamicEnergy>0.0962</DynamicEnergy>
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</BranchPredictor>
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<LSQ>
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<NumLoadEntries>72</NumLoadEntries>
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<NumStoreEntries>56</NumStoreEntries> <!--Maximum number of entries in the LSQ--><!--72 load entries, 56 store entries in skylake-->
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<LSQLatency>0</LSQLatency> <!--In clock cycles-->
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<LSQPortType>UL</LSQPortType> <!--Type of access ports in the LSQ (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
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<LSQAccessPorts>-1</LSQAccessPorts> <!--Number of access ports in the LSQ-->
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<LSQPortOccupancy>-1</LSQPortOccupancy> <!--The occupancy of the LSQ ports (in clock cycles)-->
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<LeakageEnergy>0.0318</LeakageEnergy>
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<DynamicEnergy>0.1725</DynamicEnergy>
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</LSQ>
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<ITLB>
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<Size>128</Size> <!--Maximum number of entries in the TLB-->
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<Latency>1</Latency> <!--In clock cycles-->
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<MissPenalty>-1</MissPenalty> <!--In clock cycles; -1 indicates there is another TLB level below-->
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<PortType>UL</PortType> <!--Type of access ports in the TLB (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
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<AccessPorts>-1</AccessPorts> <!--Number of access ports in the TLB-->
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<PortOccupancy>-1</PortOccupancy> <!--The occupancy of the TLB ports (in clock cycles)-->
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<LeakageEnergy>0.00546275</LeakageEnergy>
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<DynamicEnergy>0.06792852941</DynamicEnergy>
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</ITLB>
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<DTLB>
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<Size>64</Size> <!--Maximum number of entries in the TLB-->
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<Latency>1</Latency> <!--In clock cycles-->
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<MissPenalty>-1</MissPenalty> <!--In clock cycles; -1 indicates there is another TLB level below-->
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<PortType>UL</PortType> <!--Type of access ports in the TLB (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
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<AccessPorts>-1</AccessPorts> <!--Number of access ports in the TLB-->
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<PortOccupancy>-1</PortOccupancy> <!--The occupancy of the TLB ports (in clock cycles)-->
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<LeakageEnergy>0.00546275</LeakageEnergy>
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<DynamicEnergy>0.06792852941</DynamicEnergy>
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</DTLB>
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<STLB> <!-- unified second level TLB -->
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<Size>1536</Size> <!--Maximum number of entries in the TLB-->
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<Latency>9</Latency> <!--In clock cycles-->
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<MissPenalty>17</MissPenalty> <!--In clock cycles; -1 indicates there is another TLB level below-->
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<PortType>UL</PortType> <!--Type of access ports in the TLB (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
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<AccessPorts>-1</AccessPorts> <!--Number of access ports in the TLB-->
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<PortOccupancy>-1</PortOccupancy> <!--The occupancy of the TLB ports (in clock cycles)-->
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<LeakageEnergy>0.00546275</LeakageEnergy> <!-- TODO this number isn't right -->
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<DynamicEnergy>0.06792852941</DynamicEnergy> <!-- TODO this number isn't right -->
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</STLB>
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<MicroOpCache>
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<NumberOfMicroOps>2304</NumberOfMicroOps>
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</MicroOpCache>
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<Decode> <!--Instruction decode-->
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<Width>6</Width>
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<LeakageEnergy>0.0598</LeakageEnergy>
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<DynamicEnergy>0.0347</DynamicEnergy>
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</Decode>
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<Rename>
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<Width>6</Width>
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<RAT>
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<Integer>
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<LeakageEnergy>0.0045</LeakageEnergy>
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<DynamicEnergy>0.0150</DynamicEnergy>
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</Integer>
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<Float>
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<LeakageEnergy>0.0017</LeakageEnergy>
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<DynamicEnergy>0.0130</DynamicEnergy>
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</Float>
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</RAT>
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<FreeList>
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<Integer>
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<LeakageEnergy>0.0016</LeakageEnergy>
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<DynamicEnergy>0.0085</DynamicEnergy>
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</Integer>
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<Float>
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<LeakageEnergy>0.0030</LeakageEnergy>
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<DynamicEnergy>0.0045</DynamicEnergy>
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</Float>
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</FreeList>
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</Rename>
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<InstructionWindow>
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<IssueWidth>8</IssueWidth> <!--Instruction issue width-->
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<IWSize>97</IWSize> <!--Maximum number of entries in the Instruction Window-->
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<LeakageEnergy>0.0046</LeakageEnergy>
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<DynamicEnergy>0.0142</DynamicEnergy>
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</InstructionWindow>
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<ROB>
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<RetireWidth>6</RetireWidth> <!--Instruction retire width-->
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<ROBSize>224</ROBSize> <!--Maximum number of entries in the ROB-->
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<LeakageEnergy>0.0058</LeakageEnergy>
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<DynamicEnergy>0.0304</DynamicEnergy>
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</ROB>
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<RegisterFile>
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<Integer>
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<IntRegFileSize>180</IntRegFileSize> <!--Maximum number of entries in the Integer register file-->
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<IntArchRegNum>64</IntArchRegNum> <!--Number of Integer architectural registers-->
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<LeakageEnergy>0.0108</LeakageEnergy>
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<DynamicEnergy>0.0572</DynamicEnergy>
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</Integer>
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<Vector>
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<VectorRegFileSize>168</VectorRegFileSize> <!--Maximum number of entries in the Floating point register file-->
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<VectorArchRegNum>64</VectorArchRegNum> <!--Number of Floating point architectural registers-->
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<LeakageEnergy>0.0075</LeakageEnergy>
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<DynamicEnergy>0.0207</DynamicEnergy>
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</Vector>
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</RegisterFile>
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<ExecutionCoreNumPorts>8</ExecutionCoreNumPorts>
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<IntALU>
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<Num>4</Num> <!--Number of Integer ALUs-->
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<Latency>1</Latency> <!--Latency of Integer ALUs-->
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<!--PortNumber>0</PortNumber-->
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<PortNumber>5</PortNumber>
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<PortNumber>6</PortNumber>
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<LeakageEnergy>0.0542</LeakageEnergy>
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<DynamicEnergy>0.3257</DynamicEnergy>
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</IntALU>
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<IntMul>
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<Num>1</Num>
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<Latency>4</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</IntMul>
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<IntDiv>
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<Num>1</Num>
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<Latency>50</Latency>
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<ReciprocalOfThroughput>50</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</IntDiv>
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<FloatALU>
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<Num>0</Num>
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<Latency>3</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0654</LeakageEnergy>
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<DynamicEnergy>0.5366</DynamicEnergy>
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</FloatALU>
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<FloatMul>
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<Num>0</Num>
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<Latency>5</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</FloatMul>
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<FloatDiv>
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<Num>1</Num>
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<Latency>14</Latency>
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<ReciprocalOfThroughput>4</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</FloatDiv>
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<IntVectorALU>
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<Num>3</Num>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<PortNumber>5</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</IntVectorALU>
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<IntVectorMul>
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<Num>2</Num>
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<Latency>5</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</IntVectorMul>
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<FloatVectorALU>
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<Num>0</Num>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<PortNumber>5</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</FloatVectorALU>
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<FloatVectorMul>
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<Num>0</Num>
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<Latency>5</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</FloatVectorMul>
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<FMA>
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<Num>2</Num>
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<Latency>4</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</FMA>
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<AES>
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<Num>1</Num>
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<Latency>4</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</AES>
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<VectorString>
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<Num>1</Num>
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<Latency>9</Latency>
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<ReciprocalOfThroughput>5</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</VectorString>
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<BitScan>
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<Num>1</Num>
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<Latency>3</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>1</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</BitScan>
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<VectorShuffle>
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<Num>1</Num>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>5</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</VectorShuffle>
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<LEA>
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<Num>1</Num>
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<Latency>3</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>5</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</LEA>
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<Branch>
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<Num>2</Num>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>0</PortNumber>
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<PortNumber>6</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
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</Branch>
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<LoadAGU>
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<Num>2</Num>
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<Latency>1</Latency>
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<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
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<PortNumber>2</PortNumber>
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<PortNumber>3</PortNumber>
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<LeakageEnergy>0.0271</LeakageEnergy>
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<DynamicEnergy>0.6514</DynamicEnergy>
|
|
</LoadAGU>
|
|
|
|
<Load>
|
|
<Num>2</Num>
|
|
<Latency>1</Latency>
|
|
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
|
|
<PortNumber>2</PortNumber>
|
|
<PortNumber>3</PortNumber>
|
|
<LeakageEnergy>0.0271</LeakageEnergy>
|
|
<DynamicEnergy>0.6514</DynamicEnergy>
|
|
</Load>
|
|
|
|
<StoreAGU>
|
|
<Num>1</Num>
|
|
<Latency>1</Latency>
|
|
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
|
|
<PortNumber>7</PortNumber>
|
|
<LeakageEnergy>0.0271</LeakageEnergy>
|
|
<DynamicEnergy>0.6514</DynamicEnergy>
|
|
</StoreAGU>
|
|
|
|
<Store>
|
|
<Num>1</Num>
|
|
<Latency>1</Latency>
|
|
<ReciprocalOfThroughput>1</ReciprocalOfThroughput>
|
|
<PortNumber>4</PortNumber>
|
|
<LeakageEnergy>0.0271</LeakageEnergy>
|
|
<DynamicEnergy>0.6514</DynamicEnergy>
|
|
</Store>
|
|
|
|
<ResultsBroadcastBus>
|
|
<LeakageEnergy>0.0239</LeakageEnergy>
|
|
<DynamicEnergy>0.5948</DynamicEnergy>
|
|
</ResultsBroadcastBus>
|
|
|
|
<TreeBarrier>false</TreeBarrier> <!--Only for particular purposes. Otherwise keep it as false-->
|
|
<BarrierLatency>2</BarrierLatency>
|
|
<BarrierUnit>Distributed</BarrierUnit> <!--Central and distributed-->
|
|
|
|
<!--Specify all the private caches of a core here-->
|
|
|
|
<!--The caches which connect directly to the core must be specified as firstLevel caches-->
|
|
<!--In case you want to use an unified first level cache, set the cache type to unified in the cache property field-->
|
|
|
|
<!--Each cache has has a unique (name,id) pair. The (name,id) pair is used to create connections between caches-->
|
|
|
|
<!--For private caches, the id of the cache is the core-number. -->
|
|
<!--For a shared cache which may be split up, the ids are assigned from 0,1, to (numComponents-1)-->
|
|
|
|
<!--nextLevelId field is a mathematical formula which evaluates the id of the next level cache-->
|
|
<!--The id of the current cache can be specified by a special symbol $i-->
|
|
<!--It must be used if we want to generate a topology where there are multiple caches in the next level of memory hierarchy-->
|
|
|
|
<!--Example icache scenario where there are 4 cores, and 2 cores share same L2 cache-->
|
|
<!--Cache name="iCache" nextLevel="L2" nextLevelId="$i/2" firstLevel="true" type="ICache_32K_4"/-->
|
|
<!--Cache name="L2" numComponents="2" nextLevel="L3" type="L2Cache_256K_8"/-->
|
|
<!--Here core0,core1 will use L2[0] and core2,core3 will use L2[1]-->
|
|
|
|
<Cache name="I1" nextLevel="L2" firstLevel="true" type="ICache_32K_8"/>
|
|
<Cache name="L1" nextLevel="L2" firstLevel="true" type="L1Cache_32K_8"/>
|
|
<Cache name="L2" nextLevel="L3" type="L2Cache_256K_4"/>
|
|
</Core>
|
|
|
|
<SharedCaches>
|
|
<Cache name="L3" type="L3Cache_4M_8"/><!--Intel® Core™ i7-7820X X-series Processor actually has 3M L3 12-way. Changing to 4M 8-way to keep it a power of 2 (required by Tejas)-->
|
|
<Cache name="D1" type="Directory1"/>
|
|
</SharedCaches>
|
|
|
|
<Interconnect>NOC</Interconnect>
|
|
|
|
<NOC>
|
|
<NocConfigFile>/store/Documents/B_Tech/Semester_7/ACA/Assignments/Assignment_4/NocConfig.txt</NocConfigFile>
|
|
<NocSelScheme>STATIC</NocSelScheme>
|
|
<NocNumberOfBuffers>4</NocNumberOfBuffers>
|
|
<NocPortType>FCFS</NocPortType>
|
|
<NocAccessPorts>4</NocAccessPorts>
|
|
<NocPortOccupancy>1</NocPortOccupancy>
|
|
<NocLatency>1</NocLatency>
|
|
<NocOperatingFreq>2400</NocOperatingFreq>
|
|
<NocTopology>TORUS</NocTopology> <!--NOCTopology-->
|
|
<NocRoutingAlgorithm>SIMPLE</NocRoutingAlgorithm>
|
|
<NocLatencyBetweenNOCElements>2</NocLatencyBetweenNOCElements>
|
|
<NocRouterArbiter>RR_ARBITER</NocRouterArbiter>
|
|
<TechPoint>90</TechPoint>
|
|
<NocConnection>ELECTRICAL</NocConnection>
|
|
|
|
|
|
<LeakageEnergy>0.1877</LeakageEnergy>
|
|
<DynamicEnergy>2.1164</DynamicEnergy>
|
|
</NOC>
|
|
|
|
<BUS>
|
|
<Latency>30</Latency>
|
|
<LeakageEnergy>0.1877</LeakageEnergy>
|
|
<DynamicEnergy>2.1164</DynamicEnergy>
|
|
</BUS>
|
|
<MainMemoryController> <!-- These values are used when controller specified above is DRAM (not SIMPLE) -->
|
|
<rowBufferPolicy>OpenPage</rowBufferPolicy> <!-- OpenPage or ClosePage -->
|
|
<schedulingPolicy>RankThenBankRoundRobin</schedulingPolicy> <!-- RankThenBankRoundRobin or BankThenRankRoundRobin-->
|
|
<queuingStructure>PerRank</queuingStructure> <!-- PerRank or PerRankPerBank -->
|
|
<numRankPorts>1</numRankPorts>
|
|
<rankPortType>FCFS</rankPortType> <!--Type of access ports in the MainMemoryController (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<rankOccupancy>1</rankOccupancy>
|
|
<rankLatency>100</rankLatency>
|
|
<rankOperatingFrequency>3600</rankOperatingFrequency>
|
|
<numChans>2</numChans> <!-- Number of physical channels = number of memory controllers -->
|
|
<numRanks>2</numRanks> <!-- Number of Ranks per memory controller-->
|
|
<numBanks>8</numBanks> <!-- Number of Banks per Rank -->
|
|
<numRows>16384</numRows> <!-- Number of Rows per Bank -->
|
|
<numCols>2048</numCols> <!-- Number of Columns per Bank -->
|
|
<TRANSQUEUE_DEPTH>32</TRANSQUEUE_DEPTH> <!-- Depth of transaction queue. Note: currently this is not used -->
|
|
<TOTAL_ROW_ACCESSES>4</TOTAL_ROW_ACCESSES> <!-- For Open Page policy: Number of continuous row accesses after which the row would be closed. This is to prevent starvation to other rows. -->
|
|
|
|
<!-- Timing parameters follow below -->
|
|
<!-- Currently set according to DDR3 Micron 32M 8B x4 speed grade: 125 -->
|
|
<!-- Timing parameters for other devices can be found in DRAMSim2 repository in GitHub. Check folder "ini" for device specific timing parameters. Or same can be obtained from Datasheets for Micron DDR parts -->
|
|
|
|
<tCCD>4</tCCD> <!-- Column-to-Column Delay: internal burst (prefetch) length. DDR: 1, DDR2: 2, DDR2: 4-->
|
|
<tBL>8</tBL> <!-- Data burst duration i.e. number of bytes returned for each request (burst). Specified in beats not cycles. DDR3: 8 beats -->
|
|
<tCL>11</tCL> <!-- Column Access Strobe latency. Cycles between column access command and start of data return by the DRAM device -->
|
|
<tAL>0</tAL> <!-- Latency added to column accesses. Used for posted CAS commands. -->
|
|
<tRP>11</tRP> <!-- Row Precharge. Time that it takes for the array to precharge (in cycles) -->
|
|
<tCMD>1</tCMD> <!-- Command transport duration. The num of cycles a command occupies on the command bus from controller to DRAM device (Ranks) -->
|
|
<tRC>39</tRC> <!-- Row Cycle. Cycles between accesses to different rows in a bank. tRC = tRAS + tRP -->
|
|
<tRCD>11</tRCD> <!-- Row to Column command delay. Cycles between row access and date readt at sense amplifiers -->
|
|
<tRAS>28</tRAS> <!-- Row Access Strobe. Cycles between row access command and data restoration in the DRAM array. DRAM bank cannot be precharged until at least tRAS cycles after previous bank activation -->
|
|
<tRFC>88</tRFC> <!-- Refresh Cycle time. Cycles it takes to refresh the array. -->
|
|
<tRTRS>1</tRTRS> <!-- Rank to Rank switching time. Cycles required to switch from 1 rank to another rank -->
|
|
<tRRD>5</tRRD> <!-- Row activation to Row activation delay. Minimum cycles between two row activation commands to the same DRAM device. Limits peak current profile. -->
|
|
<tFAW>24</tFAW> <!-- Four (row) bank Activation Window. A rolling time-frame in which a maximum of four-bank activation can be engaged. Limits peak current profile. -->
|
|
<tRTP>6</tRTP> <!-- Rank to Precharge. Cycles between a read and a precharge command. -->
|
|
<tWTR>6</tWTR> <!-- Write to Read delay time.The minimum time interval -->
|
|
<tWR>12</tWR> <!-- Write Recovery Time. The minimum cycles between end of a write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. -->
|
|
<tCK>1.25</tCK> <!-- Clock cycle period in ns -->
|
|
<RefreshPeriod>7800</RefreshPeriod> <!-- Time (in ns) after which a Refresh is issued -->
|
|
<DATA_BUS_BITS>64</DATA_BUS_BITS> <!-- Width of DATA bus in bits. 64 bits according to JEDEC standard -->
|
|
</MainMemoryController>
|
|
|
|
</System>
|
|
|
|
<!--Give all the library elements here-->
|
|
<Library>
|
|
<UnifiedCache_32K_8>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>4000</Frequency> <!-- private caches take frequency of containing core -->
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>32768</Size> <!--In Bytes-->
|
|
<ReadLatency>3</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>3</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>16</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1092</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.33964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.33964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--Instruction,Data,Unified-->
|
|
</UnifiedCache_32K_8>
|
|
|
|
<ICache_32K_8>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2500</Frequency> <!-- private caches take frequency of containing core -->
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>32768</Size> <!--In Bytes-->
|
|
<ReadLatency>4</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>4</WriteLatency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>4</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>16</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1092</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.33964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.33964264705</WriteDynamicEnergy>
|
|
<CacheType>Instruction</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</ICache_32K_8>
|
|
|
|
<L1Cache_32K_8>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2500</Frequency> <!-- private caches take frequency of containing core -->
|
|
<WriteMode>WT</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>32768</Size> <!--In Bytes-->
|
|
<ReadLatency>4</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>4</WriteLatency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>1</ReadPorts>
|
|
<WritePorts>1</WritePorts>
|
|
<ReadWritePorts>0</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>2</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>16</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1092</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.33964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.33964264705</WriteDynamicEnergy>
|
|
<CacheType>Data</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L1Cache_32K_8>
|
|
|
|
<L2Cache_256K_8>
|
|
<AMAT>-1</AMAT>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>262144</Size> <!--In Bytes-->
|
|
<ReadLatency>12</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>12</WriteLatency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>256</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1592</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.43964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.43964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L2Cache_256K_8>
|
|
|
|
<L2Cache_256K_4>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2500</Frequency> <!-- private caches take frequency of containing core -->
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>4</Associativity>
|
|
<Size>262144</Size> <!--In Bytes-->
|
|
<ReadLatency>12</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>12</WriteLatency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>1</ReadPorts>
|
|
<WritePorts>1</WritePorts>
|
|
<ReadWritePorts>0</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>256</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1592</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.43964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.43964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L2Cache_256K_4>
|
|
|
|
<L2Cache_1M_16>
|
|
<AMAT>-1</AMAT>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>16</Associativity>
|
|
<Size>1048576</Size> <!--In Bytes-->
|
|
<Latency>12</Latency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>1</ReadPorts>
|
|
<WritePorts>1</WritePorts>
|
|
<ReadWritePorts>0</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>D1</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>256</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1592</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.43964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.43964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L2Cache_1M_16>
|
|
|
|
<L3Cache_1M_8>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2000</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>1048576</Size> <!--In Bytes-->
|
|
<ReadLatency>60</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>60</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_1M_8>
|
|
|
|
<L3Cache_8M_16><!--Intel® Core™ i7-7820X X-series Processor actually has 11M L3. Reducing to 8 to keep it a power of 2 (required by Tejas)-->
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>4000</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>16</Associativity>
|
|
<Size>8388608</Size> <!--In Bytes-->
|
|
<ReadLatency>77</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>77</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>1</ReadPorts>
|
|
<WritePorts>1</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>2</PortReadOccupancy>
|
|
<PortWriteOccupancy>2</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_8M_16>
|
|
|
|
<L3Cache_4M_8><!--Intel® Core™ i5-7200U Processor actually has 3M 12-way L3. Changing to 4M 8-way to keep it a power of 2 (required by Tejas)-->
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2500</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>8</Associativity>
|
|
<Size>4194304</Size> <!--In Bytes-->
|
|
<ReadLatency>44</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>44</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>1</ReadPorts>
|
|
<WritePorts>1</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>2</PortReadOccupancy>
|
|
<PortWriteOccupancy>2</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>Power4</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_4M_8>
|
|
|
|
<L3Cache_12M_16>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2000</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>16</Associativity>
|
|
<Size>12582912</Size> <!--In Bytes-->
|
|
<ReadLatency>60</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>60</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_12M_16>
|
|
|
|
<L3Cache_22M_16>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2000</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>16</Associativity>
|
|
<Size>23068672</Size> <!--In Bytes-->
|
|
<ReadLatency>44</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>44</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_22M_16>
|
|
|
|
<L3Cache_16M_16>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2000</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes-->
|
|
<Associativity>16</Associativity>
|
|
<Size>16777216</Size> <!--In Bytes-->
|
|
<ReadLatency>44</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>44</WriteLatency> <!--In clock cycles-->
|
|
<PortType>UL</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>1</ReadWritePorts>
|
|
<PortReadOccupancy>5</PortReadOccupancy>
|
|
<PortWriteOccupancy>5</PortWriteOccupancy>
|
|
<Coherence>None</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>8</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<LeakageEnergy>0.1892</LeakageEnergy>
|
|
<ReadDynamicEnergy>0.60964264705</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>0.60964264705</WriteDynamicEnergy>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</L3Cache_16M_16>
|
|
|
|
<Directory1>
|
|
<AMAT>-1</AMAT>
|
|
<Frequency>2400</Frequency>
|
|
<WriteMode>WB</WriteMode> <!--Write-back (WB) or write-through (WT)-->
|
|
<LastLevel>N</LastLevel> <!--Whether this is the last level in the hierarchy or not (Y for yes, N for no)-->
|
|
<BlockSize>64</BlockSize> <!--In bytes (this should be same as the block size of the Caches between those you want coherence)-->
|
|
<Associativity>64</Associativity>
|
|
<NumEntries>65536</NumEntries>
|
|
<ReadLatency>5</ReadLatency> <!--In clock cycles-->
|
|
<WriteLatency>5</WriteLatency> <!--In clock cycles-->
|
|
<PortType>FCFS</PortType> <!--Type of access ports in the Cache (UL : Unlimited; FCFS : First Come First Serve; PR : Priority port)-->
|
|
<ReadPorts>0</ReadPorts>
|
|
<WritePorts>0</WritePorts>
|
|
<ReadWritePorts>2</ReadWritePorts>
|
|
<PortReadOccupancy>1</PortReadOccupancy>
|
|
<PortWriteOccupancy>1</PortWriteOccupancy>
|
|
<Coherence>N</Coherence> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<Prefetcher>None</Prefetcher>
|
|
<NumBuses>1</NumBuses> <!--Coherence of level (N : None, S : Snoopy, D : Directory)-->
|
|
<MSHRSize>16</MSHRSize>
|
|
<BusOccupancy>0</BusOccupancy>
|
|
<Nuca>NONE</Nuca> <!--NUCA type (S_NUCA, D_NUCA, NONE)-->
|
|
<ONuca>NONE</ONuca> <!--ONUCA type (BCAST, TSI, NONE)-->
|
|
<NucaMapping>S</NucaMapping> <!--Valid for NUCA; S: Set-Associative A: Address-Mapped -->
|
|
<CacheType>Unified</CacheType>
|
|
<LeakageEnergy>.1092</LeakageEnergy>
|
|
<ReadDynamicEnergy>.3396</ReadDynamicEnergy>
|
|
<WriteDynamicEnergy>.3396</WriteDynamicEnergy>
|
|
<IsDirectory>true</IsDirectory>
|
|
<CacheType>Unified</CacheType> <!--I : Instruction, D : Data, U : Unified-->
|
|
</Directory1>
|
|
|
|
</Library>
|
|
|
|
</Configuration>
|