bug fixes related to implementation of FMA and LEA instructions

This commit is contained in:
Rajshekar K K 2021-08-08 01:32:20 +05:30
parent 32a69d259e
commit bf6d6aba33
2 changed files with 17 additions and 7 deletions

View File

@ -25,6 +25,7 @@ package emulatorinterface.translator.x86.instruction;
import emulatorinterface.translator.InvalidInstructionException; import emulatorinterface.translator.InvalidInstructionException;
import emulatorinterface.translator.x86.operand.OperandTranslator; import emulatorinterface.translator.x86.operand.OperandTranslator;
import emulatorinterface.translator.x86.registers.Registers;
import emulatorinterface.translator.x86.registers.TempRegisterNum; import emulatorinterface.translator.x86.registers.TempRegisterNum;
import generic.Instruction; import generic.Instruction;
import generic.Operand; import generic.Operand;
@ -66,10 +67,15 @@ public class FMA implements X86StaticInstructionHandler
(operand1.isFloatRegisterOperand()) && (operand1.isFloatRegisterOperand()) &&
(operand2 == null || operand2.isImmediateOperand() || operand2.isFloatRegisterOperand() || operand2.isMemoryOperand()) && (operand2 == null || operand2.isImmediateOperand() || operand2.isFloatRegisterOperand() || operand2.isMemoryOperand()) &&
(operand3 == null || operand3.isImmediateOperand() || operand3.isFloatRegisterOperand() || operand3.isMemoryOperand())) (operand3 == null || operand3.isImmediateOperand() || operand3.isFloatRegisterOperand() || operand3.isMemoryOperand()))
{ {
Operand srcOpnd1, srcOpnd2, destOpnd; /*
* FMA type instructions have 3 source operands
* VISA supports only 2 source operands
* introducing an intALU and an intermediate result to get the approximate effect
*/
Operand srcOpnd1, srcOpnd2, srcOpnd3, destOpnd;
srcOpnd1 = operand2; srcOpnd1 = operand1;
if(operand3.isMemoryOperand()) if(operand3.isMemoryOperand())
{ {
@ -79,10 +85,14 @@ public class FMA implements X86StaticInstructionHandler
{ {
srcOpnd2 = operand3; srcOpnd2 = operand3;
} }
Operand intermediateResult = Registers.getTempIntReg(tempRegisterNum);
instructionArrayList.appendInstruction(Instruction.getIntALUInstruction(srcOpnd1, srcOpnd2, intermediateResult));
srcOpnd3 = operand2;
destOpnd = operand1; destOpnd = operand1;
instructionArrayList.appendInstruction(Instruction.getFMA(srcOpnd1, srcOpnd2, destOpnd)); instructionArrayList.appendInstruction(Instruction.getFMA(intermediateResult, srcOpnd3, destOpnd));
} }
else else
@ -90,4 +100,4 @@ public class FMA implements X86StaticInstructionHandler
misc.Error.invalidOperation("Scalar FMA ", operand1, operand2, operand3); misc.Error.invalidOperation("Scalar FMA ", operand1, operand2, operand3);
} }
} }
} }

View File

@ -358,7 +358,7 @@ public class Instruction implements Serializable
Operand sourceOperand2, Operand destinationOperand) Operand sourceOperand2, Operand destinationOperand)
{ {
Instruction ins = CustomObjectPool.getInstructionPool().borrowObject(); Instruction ins = CustomObjectPool.getInstructionPool().borrowObject();
ins.set(OperationType.LEA, sourceOperand1, null, ins.set(OperationType.LEA, sourceOperand1, sourceOperand2,
destinationOperand); destinationOperand);
return ins; return ins;
} }
@ -566,4 +566,4 @@ public class Instruction implements Serializable
destinationOperandMemValue = createAddressForBM(destinationOperandMemValue, bm); destinationOperandMemValue = createAddressForBM(destinationOperandMemValue, bm);
branchTargetAddress = createAddressForBM(branchTargetAddress, bm); branchTargetAddress = createAddressForBM(branchTargetAddress, bm);
} }
} }