diff --git a/src/simulator/memorysystem/Cache.java b/src/simulator/memorysystem/Cache.java
index 063c465..a1a8950 100755
--- a/src/simulator/memorysystem/Cache.java
+++ b/src/simulator/memorysystem/Cache.java
@@ -122,6 +122,17 @@ public class Cache extends SimulationElement {
 		return mshr.isMSHRFull(addr);
 	}
 	
+	private int maximumNumberOfOutstandingWrites;
+	protected int numberOfOutstandingWrites;
+	public void incrementNumberOfOutstandingWrites()
+	{
+		numberOfOutstandingWrites++;
+	}
+	public boolean canCacheAcceptWriteRequest()
+	{
+		return (numberOfOutstandingWrites < maximumNumberOfOutstandingWrites);
+	}
+	
 	public Cache(String cacheName, int id, CacheConfig cacheParameters,
 			CoreMemorySystem containingMemSys) {
 		
@@ -210,6 +221,7 @@ public class Cache extends SimulationElement {
 		makeCache(cacheParameters.isDirectory);
 
 		this.mshr = new MSHR(cacheConfig.mshrSize, blockSizeBits, this);
+		maximumNumberOfOutstandingWrites = cacheConfig.mshrSize;
 
 		this.nucaType = cacheParameters.nucaType;
 
@@ -257,6 +269,10 @@ public class Cache extends SimulationElement {
 		
 		noOfAccesses++;
 		
+		if (requestType == RequestType.Cache_Write) {
+			numberOfOutstandingWrites--;
+		}
+		
 		if(mshr.isAddrInMSHR(addr) && 
 			(requestType==RequestType.Cache_Read || requestType==RequestType.Cache_Write || requestType==RequestType.EvictCacheLine)) {
 			if(requestType==RequestType.Cache_Read || requestType==RequestType.Cache_Write)
@@ -493,6 +509,10 @@ public class Cache extends SimulationElement {
 				event = new AddressCarryingEvent(c.getEventQueue(), 0, this, c,
 						requestType, addr);
 				addEventAtLowerCache(event, c);
+				if(requestType == RequestType.Cache_Write)
+				{
+					c.incrementNumberOfOutstandingWrites();
+				}
 			}
 		} else {
 			Core core0 = ArchitecturalComponent.getCores()[0];
diff --git a/src/simulator/pipeline/multi_issue_inorder/InorderCoreMemorySystem_MII.java b/src/simulator/pipeline/multi_issue_inorder/InorderCoreMemorySystem_MII.java
index 2df5972..860a20c 100755
--- a/src/simulator/pipeline/multi_issue_inorder/InorderCoreMemorySystem_MII.java
+++ b/src/simulator/pipeline/multi_issue_inorder/InorderCoreMemorySystem_MII.java
@@ -6,6 +6,7 @@ import generic.Event;
 import generic.EventQueue;
 import generic.RequestType;
 import memorysystem.AddressCarryingEvent;
+import memorysystem.Cache;
 import memorysystem.CoreMemorySystem;
 
 public class InorderCoreMemorySystem_MII extends CoreMemorySystem {
@@ -48,6 +49,18 @@ public class InorderCoreMemorySystem_MII extends CoreMemorySystem {
 		if(l1Cache.isBusy(address)) {
 			return false;
 		}
+		if(requestType == RequestType.Cache_Write)
+		{
+			Cache c = l1Cache;
+			while(c != null)
+			{
+				if(c.canCacheAcceptWriteRequest() == false)
+					return false;
+				
+				c = c.nextLevel;
+			}
+			this.l1Cache.incrementNumberOfOutstandingWrites();
+		}
 		
 		this.l1Cache.getPort().put(addressEvent);
 		
diff --git a/src/simulator/pipeline/outoforder/OutOrderCoreMemorySystem.java b/src/simulator/pipeline/outoforder/OutOrderCoreMemorySystem.java
index b7c10aa..3d8c465 100755
--- a/src/simulator/pipeline/outoforder/OutOrderCoreMemorySystem.java
+++ b/src/simulator/pipeline/outoforder/OutOrderCoreMemorySystem.java
@@ -9,6 +9,7 @@ import generic.RequestType;
 import generic.SimulationElement;
 import main.ArchitecturalComponent;
 import memorysystem.AddressCarryingEvent;
+import memorysystem.Cache;
 import memorysystem.CoreMemorySystem;
 import memorysystem.LSQEntryContainingEvent;
 import memorysystem.coherence.Directory;
@@ -109,6 +110,18 @@ public class OutOrderCoreMemorySystem extends CoreMemorySystem {
 		if(l1Cache.isBusy(address)) {
 			return false;
 		}
+		if(requestType == RequestType.Cache_Write)
+		{
+			Cache c = l1Cache;
+			while(c != null)
+			{
+				if(c.canCacheAcceptWriteRequest() == false)
+					return false;
+				
+				c = c.nextLevel;
+			}
+			this.l1Cache.incrementNumberOfOutstandingWrites();
+		}
 		
 		this.l1Cache.getPort().put(addressEvent);