added instruction serial number in outoforder pipeline
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parent
178dfd7a63
commit
5a4be62352
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@ -530,6 +530,7 @@ public class Instruction implements Serializable
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{
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{
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return
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return
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(
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(
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String.format("%-20s", "s.no = " + serialNo) +
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String.format("%-20s", "IP = " + Long.toHexString(ciscProgramCounter)) +
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String.format("%-20s", "IP = " + Long.toHexString(ciscProgramCounter)) +
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String.format("%-20s", "Op = " + type) +
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String.format("%-20s", "Op = " + type) +
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String.format("%-60s", "srcOp1 = " + sourceOperand1) +
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String.format("%-60s", "srcOp1 = " + sourceOperand1) +
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@ -30,6 +30,8 @@ public class FetchLogic extends SimulationElement {
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OperationType[] instructionsToBeDropped;
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OperationType[] instructionsToBeDropped;
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boolean sleep;
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boolean sleep;
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long serialNo;
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public FetchLogic(Core core, OutOrderExecutionEngine execEngine)
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public FetchLogic(Core core, OutOrderExecutionEngine execEngine)
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{
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{
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super(PortType.Unlimited, -1, -1, -1, -1);
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super(PortType.Unlimited, -1, -1, -1, -1);
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@ -44,6 +46,8 @@ public class FetchLogic extends SimulationElement {
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OperationType.interrupt,
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OperationType.interrupt,
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OperationType.sync
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OperationType.sync
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};
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};
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serialNo = 0;
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}
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}
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public void performFetch()
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public void performFetch()
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@ -182,6 +186,7 @@ public class FetchLogic extends SimulationElement {
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if(!iCacheBuffer.isFull() && execEngine.getCoreMemorySystem().getiCache().isBusy(newInstruction.getCISCProgramCounter())==false)
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if(!iCacheBuffer.isFull() && execEngine.getCoreMemorySystem().getiCache().isBusy(newInstruction.getCISCProgramCounter())==false)
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{
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{
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iCacheBuffer.addToBuffer(inputToPipeline[inputPipeToReadNext].pollFirst());
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iCacheBuffer.addToBuffer(inputToPipeline[inputPipeToReadNext].pollFirst());
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newInstruction.setSerialNo(serialNo++);
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if(SimulationConfig.detachMemSysInsn == false && newInstruction.getOperationType() != OperationType.inValid)
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if(SimulationConfig.detachMemSysInsn == false && newInstruction.getOperationType() != OperationType.inValid)
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{
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{
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// The first micro-operation of an instruction has a valid CISC IP. All the subsequent
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// The first micro-operation of an instruction has a valid CISC IP. All the subsequent
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