added instruction serial number in outoforder pipeline
This commit is contained in:
		
							parent
							
								
									178dfd7a63
								
							
						
					
					
						commit
						5a4be62352
					
				| 
						 | 
				
			
			@ -530,6 +530,7 @@ public class Instruction implements Serializable
 | 
			
		|||
	{
 | 
			
		||||
		return 
 | 
			
		||||
		(
 | 
			
		||||
			String.format("%-20s", "s.no = " + serialNo) +
 | 
			
		||||
			String.format("%-20s", "IP = " + Long.toHexString(ciscProgramCounter)) +
 | 
			
		||||
			String.format("%-20s", "Op = " + type) +
 | 
			
		||||
			String.format("%-60s", "srcOp1 = " + sourceOperand1) +
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
| 
						 | 
				
			
			@ -29,6 +29,8 @@ public class FetchLogic extends SimulationElement {
 | 
			
		|||
	int fetchWidth;
 | 
			
		||||
	OperationType[] instructionsToBeDropped;
 | 
			
		||||
	boolean sleep;
 | 
			
		||||
	
 | 
			
		||||
	long serialNo;
 | 
			
		||||
 | 
			
		||||
	public FetchLogic(Core core, OutOrderExecutionEngine execEngine)
 | 
			
		||||
	{
 | 
			
		||||
| 
						 | 
				
			
			@ -44,6 +46,8 @@ public class FetchLogic extends SimulationElement {
 | 
			
		|||
															OperationType.interrupt,
 | 
			
		||||
															OperationType.sync
 | 
			
		||||
													};
 | 
			
		||||
		
 | 
			
		||||
		serialNo = 0;
 | 
			
		||||
	}
 | 
			
		||||
	
 | 
			
		||||
	public void performFetch()
 | 
			
		||||
| 
						 | 
				
			
			@ -182,6 +186,7 @@ public class FetchLogic extends SimulationElement {
 | 
			
		|||
			if(!iCacheBuffer.isFull() && execEngine.getCoreMemorySystem().getiCache().isBusy(newInstruction.getCISCProgramCounter())==false)
 | 
			
		||||
			{
 | 
			
		||||
				iCacheBuffer.addToBuffer(inputToPipeline[inputPipeToReadNext].pollFirst());
 | 
			
		||||
				newInstruction.setSerialNo(serialNo++);
 | 
			
		||||
				if(SimulationConfig.detachMemSysInsn == false && newInstruction.getOperationType() != OperationType.inValid)
 | 
			
		||||
				{
 | 
			
		||||
						// The first micro-operation of an instruction has a valid CISC IP. All the subsequent 
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
		Reference in New Issue