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EmbeddedLab2023
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base: kabhijit:GPIO-ISR-Testing
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kabhijit:GPIO_ISR_Debug
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kabhijit:GPIO-ISR-Testing
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kabhijit:GPIO_ISR_Debug
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kabhijit:GPIO-ISR-Testing

2 Commits
GPIO-ISR-T ... master

Author SHA1 Message Date
Abhijit Kshirsagar Kshirsagar 9aedf55e32 Add NOP to give time for ICR register write 2023-09-04 19:38:48 +05:30
Abhijit Kshirsagar Kshirsagar 5f32671262 Add both SW1 and SW2 Interrupts 2023-09-04 12:44:36 +05:30
1 changed files with 19 additions and 3 deletions
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GPIO_Interrupts/main.c
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@ -26,8 +26,20 @@ int main(void)
void SW2_Handler(void)
{
GPIO_PORTF_DATA_R ^= 0x8;
GPIO_PORTF_ICR_R = 0xff;
//GPIO_PORTF_ICR_R = 0x11;
if(GPIO_PORTF_MIS_R & 0x01)
{
//PIN0 (SW2) pressed
GPIO_PORTF_DATA_R |= 0x8;
}
else if (GPIO_PORTF_MIS_R & 0x10)
{
GPIO_PORTF_DATA_R &= ~0x8;
}
GPIO_PORTF_ICR_R = 0x11;
__asm(" nop");
}
@ -58,6 +70,10 @@ void GPIO_PORTF_Init(void)
//Need to enable interrupt on SW1
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOF;
GPIO_PORTF_LOCK_R = 0x4C4F434B; /* unlock commit register */
GPIO_PORTF_CR_R = 0xFF; /* make PORTF0 configurable */
GPIO_PORTF_DEN_R = 0x1F;
GPIO_PORTF_PUR_R = 0x11;
GPIO_PORTF_DIR_R = 0x0E;
@ -80,7 +96,7 @@ void GPIO_PORTF_Init(void)
GPIO_PORTF_ICR_R = 0xff;
//GPIOIM -- Interrupt Mask --> 1 for unmasked (enabled)--> 0x01
GPIO_PORTF_IM_R = 0x10;
GPIO_PORTF_IM_R = 0x11;
//GPIORIS -- Raw Int Status
//GPIOMIS -- Masked Int Status