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Add 'gSchemHierarchicalSchematics'

Abhijit Kshirsagar Kshirsagar 2021-07-13 17:02:06 +05:30
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# Hierarchical Design
###### What is hierarchy in electronics design?
A system which allows multiple levels of abstraction of systems and components, which aids reuse, modularity and collaboration in the design process.
## Hierarchy in gEDA
The various tools of the gEDA family support hierarchy in the following ways:
### gSchem
It is possible to abstract an entire schematic into a single symbol which can be used for higher level schematics. To create a symbol from a given schematic, one can use a tool such as [geda_sch2sym](geda_sch2sym), or create a symbol [manually](gSchem Symbols#Hierarchical_Symbols). gschem allows the user to navigate the hierarchy from the Hierarchy menu.
The '''source=''' attribute must be the name (not path) of the schematic the symbol points to. The location of the sub-schematic should be made known to gschem using the source-library directive via an appropriate gafrc file.
## [gnetlist supports two modes of netlisting - with hierarchy traversal enabled or disabled.
### Hierarchy Traversal Enabled
In this case we let gnetlist traverse the entire design hierarchy and create a single flattened netlist. The hierarchy traversal option may need to be enforced using a gnetlistrc file if not enabled by default. In this case the subschematic must have IO connections denoted by IO devices which have the REFDES matching the pinlabel on the top level symbol.
### Hierarchy Traversal Disabled
In this case we netlist each schematic separately (the lower level schematics first). Hierarchy traversal may need to be disabled using a gnetlistrc file if not disabled by default. In this case the subschematic must have IO connections denoted the spice-subckt-io devices and the top level symbol must have attributes model-name (pointing to the name of the subcircuit) and the attribute "file=" pointing to a file containing the netlisted subcircuit. In this case the gnetlist backend spice-sdb must be used for netlisting.
# References
#An excellent reference is [[File:Hierarchical_and_Multi_Page_Designs_HOWTO_-_Kaiser.pdf | this pdf by Peter Kaiser.]([gnetlist]])]
#A thread on the gEDA Wiki: [#Also see the tool [[Geda_sch2sym](http://wiki.geda-project.org/geda:faq-gschem#can_gschem_do_hierarchical_designs_with_sub_sheets])]
#A patch for spice-sdb that is able to generate subcircuit definitions with the parameter default values [https://bugs.launchpad.net/geda/+bug/698736]