From 7ff54a38e05312f7f10560696fe6ba1392ced72c Mon Sep 17 00:00:00 2001 From: Uttam Bhavimani Bhavimani Date: Fri, 29 Nov 2024 14:44:01 +0530 Subject: [PATCH] Remove Port F interrupt --- main.c | 89 +++++++++++++++++++++++++++------------------------------- 1 file changed, 42 insertions(+), 47 deletions(-) diff --git a/main.c b/main.c index 90f635a..c81aa5b 100644 --- a/main.c +++ b/main.c @@ -1,47 +1,42 @@ -#include -#include -#include "tm4c123gh6pm.h" - -void GPIO_PORT_F_init(void) -{ - SYSCTL_RCGC2_R |= 0x00000020; // ENABLE CLOCK TO GPIOF - GPIO_PORTF_LOCK_R = 0x4C4F434B; // UNLOCK COMMIT REGISTER - GPIO_PORTF_CR_R = 0x1F; // MAKE PORTF0 CONFIGURABLE - GPIO_PORTF_DEN_R = 0x1F; // SET PORTF DIGITAL ENABLE - GPIO_PORTF_DIR_R = 0x0E; // SET PF0, PF4 as input and PF1, PF2 and PF3 as output - GPIO_PORTF_PUR_R = 0x11; // PORTF PF0 and PF4 IS PULLED UP - - NVIC_EN0_R |= 1 << 30; - GPIO_PORTF_IS_R = 0x00; // EDGE SENSITIVE - GPIO_PORTF_IBE_R = 0x00; // ONE EDGE - GPIO_PORTF_IEV_R = 0x00; // INTERRUPT EVENT FALLING - GPIO_PORTF_IM_R |= 0x11; // UNMASK INTERRUPT -} - - -void GPIO_PORT_B_init(void) -{ - - SYSCTL_RCGCGPIO_R |= 0x02; // ENABLE CLOCK FOR GPIOB - SYSCTL_RCGCUART_R |= 0x02; // ENABLE CLOCK FOR UART1 - - GPIO_PORTB_DEN_R |= 0x03; // DIGITAL ENABLE FOR PB0 AND PB1 - GPIO_PORTB_AFSEL_R |= 0x03; // ENABLE ALTERNATE FUNCTION ON PB0,PB1 - - GPIO_PORTB_PCTL_R = (GPIO_PORTB_PCTL_R & 0xFFFFFF00) | 0x00000011; // Set PB0, PB1 for UART - - UART1_CTL_R &= ~0x01; // DISABLE UART1 DURING SETUP - UART1_IBRD_R = 104; // Set integer part of baud rate (for 9600 baud at 16 MHz clock) - UART1_FBRD_R = 11; // Set fractional part of baud rate - UART1_LCRH_R = 0x62; // 8-bit, odd parity, 1 stop bit - UART1_CC_R = 0x00; // Use system clock - - UART1_CTL_R |= 0x301; // Enable UART1, RX, and TX - -} - -char UART1_READ(void) -{ - while (UART1_FR_R & 0x10); // Wait until RX FIFO is not empty - return (char)UART1_DR_R; // Return received data -} +#include +#include +#include "tm4c123gh6pm.h" + +void GPIO_PORT_F_init(void) +{ + SYSCTL_RCGC2_R |= 0x00000020; // ENABLE CLOCK TO GPIOF + GPIO_PORTF_LOCK_R = 0x4C4F434B; // UNLOCK COMMIT REGISTER + GPIO_PORTF_CR_R = 0x1F; // MAKE PORTF0 CONFIGURABLE + GPIO_PORTF_DEN_R = 0x1F; // SET PORTF DIGITAL ENABLE + GPIO_PORTF_DIR_R = 0x0E; // SET PF0, PF4 as input and PF1, PF2 and PF3 as output + GPIO_PORTF_PUR_R = 0x11; // PORTF PF0 and PF4 IS PULLED UP + +} + + +void GPIO_PORT_B_init(void) +{ + + SYSCTL_RCGCGPIO_R |= 0x02; // ENABLE CLOCK FOR GPIOB + SYSCTL_RCGCUART_R |= 0x02; // ENABLE CLOCK FOR UART1 + + GPIO_PORTB_DEN_R |= 0x03; // DIGITAL ENABLE FOR PB0 AND PB1 + GPIO_PORTB_AFSEL_R |= 0x03; // ENABLE ALTERNATE FUNCTION ON PB0,PB1 + + GPIO_PORTB_PCTL_R = (GPIO_PORTB_PCTL_R & 0xFFFFFF00) | 0x00000011; // Set PB0, PB1 for UART + + UART1_CTL_R &= ~0x01; // DISABLE UART1 DURING SETUP + UART1_IBRD_R = 104; // Set integer part of baud rate (for 9600 baud at 16 MHz clock) + UART1_FBRD_R = 11; // Set fractional part of baud rate + UART1_LCRH_R = 0x62; // 8-bit, odd parity, 1 stop bit + UART1_CC_R = 0x00; // Use system clock + + UART1_CTL_R |= 0x301; // Enable UART1, RX, and TX + +} + +char UART1_READ(void) +{ + while (UART1_FR_R & 0x10); // Wait until RX FIFO is not empty + return (char)UART1_DR_R; // Return received data +}