From d110658f1267d0037ea875bc7d3315c09e5861b6 Mon Sep 17 00:00:00 2001 From: Uttam Ambappa Bhavimani Date: Mon, 28 Oct 2024 22:51:49 +0530 Subject: [PATCH] Update main.c Initialize GPIO Port B --- main.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/main.c b/main.c index 8a5bce8..03a87b6 100644 --- a/main.c +++ b/main.c @@ -16,4 +16,25 @@ void GPIO_PORT_F_init(void) GPIO_PORTF_IBE_R = 0x00; // ONE EDGE GPIO_PORTF_IEV_R = 0x00; // INTERRUPT EVENT FALLING GPIO_PORTF_IM_R |= 0x11; // UNMASK INTERRUPT +} + +void GPIO_PORT_B_init(void) +{ + + SYSCTL_RCGCGPIO_R |= 0x02; // ENABLE CLOCK FOR GPIOB + SYSCTL_RCGCUART_R |= 0x02; // ENABLE CLOCK FOR UART1 + + GPIO_PORTB_DEN_R |= 0x03; // DIGITAL ENABLE FOR PB0 AND PB1 + GPIO_PORTB_AFSEL_R |= 0x03; // ENABLE ALTERNATE FUNCTION ON PB0,PB1 + + GPIO_PORTB_PCTL_R = (GPIO_PORTB_PCTL_R & 0xFFFFFF00) | 0x00000011; // SET PB0, PB1 FOR UART FUNCTIONALITY + + UART1_CTL_R &= ~0x01; // DISABLE UART1 DURING SETUP + UART1_IBRD_R = 104; // SET INTEGER PART OF BAUD RED FOR 9600 BAUD FORMULA: + UART1_FBRD_R = 11; // SET FRACTIONAL PART OF BAUD RATE + UART1_LCRH_R = 0x62; // SET 8-BIT, ODD PARITY, STOP BIT-1 + UART1_CC_R = 0x00; // USE SYSTEM CLOCK + + UART1_CTL_R |= 0x301; // ENABLE UART1, RX AND TX + } \ No newline at end of file