Add GPIO Port B initialize

This commit is contained in:
Sanyog Nevase Nevase 2024-10-10 20:04:27 +05:30
parent 1050494f56
commit 9eb0cee283
1 changed files with 25 additions and 0 deletions

25
main.c
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@ -18,6 +18,31 @@ void GPIO_PORT_F_init(void)
GPIO_PORTF_IM_R |= 0x11; // Unmask interrupts for PF0 and PF4 GPIO_PORTF_IM_R |= 0x11; // Unmask interrupts for PF0 and PF4
} }
void GPIO_PORT_B_init(void)
{
SYSCTL_RCGCGPIO_R |= 0x02; // Enable clock to GPIOB
SYSCTL_RCGCUART_R |= 0x02; // Enable UART1 clock
GPIO_PORTB_DEN_R |= 0x03; // Enable PB0, PB1 as digital
GPIO_PORTB_AFSEL_R |= 0x03; // Enable alternate function on PB0, PB1
GPIO_PORTB_PCTL_R = (GPIO_PORTB_PCTL_R & 0xFFFFFF00) | 0x00000011; // Set PB0, PB1 for UART
UART1_CTL_R &= ~0x01; // Disable UART1 during setup
UART1_IBRD_R = 104; // Set integer part of baud rate (for 9600 baud at 16 MHz clock)
UART1_FBRD_R = 11; // Set fractional part of baud rate
UART1_LCRH_R = 0x62; // 8-bit, odd parity, 1 stop bit
UART1_CC_R = 0x00; // Use system clock
UART1_CTL_R |= 0x301; // Enable UART1, RX, and TX
}
void UART1_WRITE(char data) void UART1_WRITE(char data)
{ {
while (UART1_FR_R & 0x20); // Wait until TX FIFO is not full while (UART1_FR_R & 0x20); // Wait until TX FIFO is not full