Update vector table
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@ -1,300 +1,302 @@
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//*****************************************************************************
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//*****************************************************************************
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//
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//
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// Startup code for use with TI's Code Composer Studio.
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// Startup code for use with TI's Code Composer Studio.
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//
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//
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// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved.
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// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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// Software License Agreement
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//
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//
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// Software License Agreement
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// Software License Agreement
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//
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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// software in order to form a larger program.
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//
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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//
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//*****************************************************************************
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//*****************************************************************************
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#include <stdint.h>
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#include <stdint.h>
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//*****************************************************************************
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//*****************************************************************************
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//
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//
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// Forward declaration of the default fault handlers.
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// Forward declaration of the default fault handlers.
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//
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//
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//*****************************************************************************
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//*****************************************************************************
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void ResetISR(void);
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void ResetISR(void);
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static void NmiSR(void);
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static void NmiSR(void);
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static void FaultISR(void);
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static void FaultISR(void);
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static void IntDefaultHandler(void);
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static void IntDefaultHandler(void);
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void SystickHandler(void);
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//*****************************************************************************
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void GPIOF_interruptHandler(void);
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//
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//*****************************************************************************
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// External declaration for the reset handler that is to be called when the
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//
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// processor is started
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// External declaration for the reset handler that is to be called when the
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//
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// processor is started
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//*****************************************************************************
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//
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extern void _c_int00(void);
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//*****************************************************************************
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extern void _c_int00(void);
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//*****************************************************************************
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//
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//*****************************************************************************
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// Linker variable that marks the top of the stack.
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//
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//
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// Linker variable that marks the top of the stack.
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//*****************************************************************************
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//
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extern uint32_t __STACK_TOP;
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//*****************************************************************************
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extern uint32_t __STACK_TOP;
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//*****************************************************************************
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//
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//*****************************************************************************
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// External declarations for the interrupt handlers used by the application.
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//
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//
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// External declarations for the interrupt handlers used by the application.
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//*****************************************************************************
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//
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// To be added by user
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//*****************************************************************************
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// To be added by user
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//*****************************************************************************
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extern void SystickHandler(void);
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//
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extern void GPIOF_interruptHandler(void);
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// The vector table. Note that the proper constructs must be placed on this to
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//*****************************************************************************
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// ensure that it ends up at physical address 0x0000.0000 or at the start of
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//
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// the program if located at a start address other than 0.
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// The vector table. Note that the proper constructs must be placed on this to
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//
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// ensure that it ends up at physical address 0x0000.0000 or at the start of
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//*****************************************************************************
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// the program if located at a start address other than 0.
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#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
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//
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void (* const g_pfnVectors[])(void) =
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//*****************************************************************************
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{
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#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
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(void (*)(void))((uint32_t)&__STACK_TOP),
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void (* const g_pfnVectors[])(void) =
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// The initial stack pointer
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{
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ResetISR, // The reset handler
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(void (*)(void))((uint32_t)&__STACK_TOP),
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NmiSR, // The NMI handler
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// The initial stack pointer
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FaultISR, // The hard fault handler
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ResetISR, // The reset handler
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IntDefaultHandler, // The MPU fault handler
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NmiSR, // The NMI handler
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IntDefaultHandler, // The bus fault handler
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FaultISR, // The hard fault handler
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IntDefaultHandler, // The usage fault handler
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IntDefaultHandler, // The MPU fault handler
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0, // Reserved
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IntDefaultHandler, // The bus fault handler
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0, // Reserved
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IntDefaultHandler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // SVCall handler
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0, // Reserved
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IntDefaultHandler, // Debug monitor handler
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // SVCall handler
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IntDefaultHandler, // The PendSV handler
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IntDefaultHandler, // Debug monitor handler
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IntDefaultHandler, // The SysTick handler
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0, // Reserved
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IntDefaultHandler, // GPIO Port A
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IntDefaultHandler, // The PendSV handler
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IntDefaultHandler, // GPIO Port B
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SystickHandler, // The SysTick handler
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IntDefaultHandler, // GPIO Port C
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IntDefaultHandler, // GPIO Port A
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IntDefaultHandler, // GPIO Port D
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IntDefaultHandler, // GPIO Port B
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IntDefaultHandler, // GPIO Port E
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IntDefaultHandler, // GPIO Port C
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IntDefaultHandler, // UART0 Rx and Tx
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IntDefaultHandler, // GPIO Port D
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IntDefaultHandler, // UART1 Rx and Tx
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IntDefaultHandler, // GPIO Port E
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IntDefaultHandler, // SSI0 Rx and Tx
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IntDefaultHandler, // UART0 Rx and Tx
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IntDefaultHandler, // I2C0 Master and Slave
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IntDefaultHandler, // UART1 Rx and Tx
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IntDefaultHandler, // PWM Fault
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IntDefaultHandler, // SSI0 Rx and Tx
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IntDefaultHandler, // PWM Generator 0
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IntDefaultHandler, // I2C0 Master and Slave
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IntDefaultHandler, // PWM Generator 1
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IntDefaultHandler, // PWM Fault
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IntDefaultHandler, // PWM Generator 2
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IntDefaultHandler, // PWM Generator 0
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IntDefaultHandler, // Quadrature Encoder 0
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IntDefaultHandler, // PWM Generator 1
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IntDefaultHandler, // ADC Sequence 0
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IntDefaultHandler, // PWM Generator 2
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IntDefaultHandler, // ADC Sequence 1
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IntDefaultHandler, // Quadrature Encoder 0
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IntDefaultHandler, // ADC Sequence 2
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IntDefaultHandler, // ADC Sequence 0
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IntDefaultHandler, // ADC Sequence 3
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IntDefaultHandler, // ADC Sequence 1
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IntDefaultHandler, // Watchdog timer
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IntDefaultHandler, // ADC Sequence 2
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IntDefaultHandler, // Timer 0 subtimer A
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IntDefaultHandler, // ADC Sequence 3
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IntDefaultHandler, // Timer 0 subtimer B
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IntDefaultHandler, // Watchdog timer
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IntDefaultHandler, // Timer 1 subtimer A
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IntDefaultHandler, // Timer 0 subtimer A
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IntDefaultHandler, // Timer 1 subtimer B
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IntDefaultHandler, // Timer 0 subtimer B
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IntDefaultHandler, // Timer 2 subtimer A
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IntDefaultHandler, // Timer 1 subtimer A
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IntDefaultHandler, // Timer 2 subtimer B
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IntDefaultHandler, // Timer 1 subtimer B
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IntDefaultHandler, // Analog Comparator 0
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IntDefaultHandler, // Timer 2 subtimer A
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IntDefaultHandler, // Analog Comparator 1
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IntDefaultHandler, // Timer 2 subtimer B
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IntDefaultHandler, // Analog Comparator 2
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IntDefaultHandler, // Analog Comparator 0
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IntDefaultHandler, // System Control (PLL, OSC, BO)
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IntDefaultHandler, // Analog Comparator 1
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IntDefaultHandler, // FLASH Control
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IntDefaultHandler, // Analog Comparator 2
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IntDefaultHandler, // GPIO Port F
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IntDefaultHandler, // System Control (PLL, OSC, BO)
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IntDefaultHandler, // GPIO Port G
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IntDefaultHandler, // FLASH Control
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IntDefaultHandler, // GPIO Port H
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GPIOF_interruptHandler, // GPIO Port F
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IntDefaultHandler, // UART2 Rx and Tx
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IntDefaultHandler, // GPIO Port G
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IntDefaultHandler, // SSI1 Rx and Tx
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IntDefaultHandler, // GPIO Port H
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IntDefaultHandler, // Timer 3 subtimer A
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IntDefaultHandler, // UART2 Rx and Tx
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IntDefaultHandler, // Timer 3 subtimer B
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IntDefaultHandler, // SSI1 Rx and Tx
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IntDefaultHandler, // I2C1 Master and Slave
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IntDefaultHandler, // Timer 3 subtimer A
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IntDefaultHandler, // Quadrature Encoder 1
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IntDefaultHandler, // Timer 3 subtimer B
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IntDefaultHandler, // CAN0
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IntDefaultHandler, // I2C1 Master and Slave
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IntDefaultHandler, // CAN1
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IntDefaultHandler, // Quadrature Encoder 1
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0, // Reserved
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IntDefaultHandler, // CAN0
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0, // Reserved
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IntDefaultHandler, // CAN1
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IntDefaultHandler, // Hibernate
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0, // Reserved
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IntDefaultHandler, // USB0
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0, // Reserved
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IntDefaultHandler, // PWM Generator 3
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IntDefaultHandler, // Hibernate
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IntDefaultHandler, // uDMA Software Transfer
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IntDefaultHandler, // USB0
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IntDefaultHandler, // uDMA Error
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IntDefaultHandler, // PWM Generator 3
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IntDefaultHandler, // ADC1 Sequence 0
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IntDefaultHandler, // uDMA Software Transfer
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IntDefaultHandler, // ADC1 Sequence 1
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IntDefaultHandler, // uDMA Error
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IntDefaultHandler, // ADC1 Sequence 2
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IntDefaultHandler, // ADC1 Sequence 0
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IntDefaultHandler, // ADC1 Sequence 3
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IntDefaultHandler, // ADC1 Sequence 1
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0, // Reserved
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IntDefaultHandler, // ADC1 Sequence 2
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0, // Reserved
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IntDefaultHandler, // ADC1 Sequence 3
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IntDefaultHandler, // GPIO Port J
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0, // Reserved
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IntDefaultHandler, // GPIO Port K
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0, // Reserved
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IntDefaultHandler, // GPIO Port L
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IntDefaultHandler, // GPIO Port J
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IntDefaultHandler, // SSI2 Rx and Tx
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IntDefaultHandler, // GPIO Port K
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IntDefaultHandler, // SSI3 Rx and Tx
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IntDefaultHandler, // GPIO Port L
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IntDefaultHandler, // UART3 Rx and Tx
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IntDefaultHandler, // SSI2 Rx and Tx
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IntDefaultHandler, // UART4 Rx and Tx
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IntDefaultHandler, // SSI3 Rx and Tx
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IntDefaultHandler, // UART5 Rx and Tx
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IntDefaultHandler, // UART3 Rx and Tx
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IntDefaultHandler, // UART6 Rx and Tx
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IntDefaultHandler, // UART4 Rx and Tx
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IntDefaultHandler, // UART7 Rx and Tx
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IntDefaultHandler, // UART5 Rx and Tx
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0, // Reserved
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IntDefaultHandler, // UART6 Rx and Tx
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0, // Reserved
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IntDefaultHandler, // UART7 Rx and Tx
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // I2C2 Master and Slave
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0, // Reserved
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IntDefaultHandler, // I2C3 Master and Slave
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0, // Reserved
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IntDefaultHandler, // Timer 4 subtimer A
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IntDefaultHandler, // I2C2 Master and Slave
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IntDefaultHandler, // Timer 4 subtimer B
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IntDefaultHandler, // I2C3 Master and Slave
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0, // Reserved
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IntDefaultHandler, // Timer 4 subtimer A
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0, // Reserved
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IntDefaultHandler, // Timer 4 subtimer B
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // Timer 5 subtimer A
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0, // Reserved
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IntDefaultHandler, // Timer 5 subtimer B
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0, // Reserved
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IntDefaultHandler, // Wide Timer 0 subtimer A
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IntDefaultHandler, // Timer 5 subtimer A
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IntDefaultHandler, // Wide Timer 0 subtimer B
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IntDefaultHandler, // Timer 5 subtimer B
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IntDefaultHandler, // Wide Timer 1 subtimer A
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IntDefaultHandler, // Wide Timer 0 subtimer A
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IntDefaultHandler, // Wide Timer 1 subtimer B
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IntDefaultHandler, // Wide Timer 0 subtimer B
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IntDefaultHandler, // Wide Timer 2 subtimer A
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IntDefaultHandler, // Wide Timer 1 subtimer A
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IntDefaultHandler, // Wide Timer 2 subtimer B
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IntDefaultHandler, // Wide Timer 1 subtimer B
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IntDefaultHandler, // Wide Timer 3 subtimer A
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IntDefaultHandler, // Wide Timer 2 subtimer A
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IntDefaultHandler, // Wide Timer 3 subtimer B
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IntDefaultHandler, // Wide Timer 2 subtimer B
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IntDefaultHandler, // Wide Timer 4 subtimer A
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IntDefaultHandler, // Wide Timer 3 subtimer A
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IntDefaultHandler, // Wide Timer 4 subtimer B
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IntDefaultHandler, // Wide Timer 3 subtimer B
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IntDefaultHandler, // Wide Timer 5 subtimer A
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IntDefaultHandler, // Wide Timer 4 subtimer A
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IntDefaultHandler, // Wide Timer 5 subtimer B
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IntDefaultHandler, // Wide Timer 4 subtimer B
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IntDefaultHandler, // FPU
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IntDefaultHandler, // Wide Timer 5 subtimer A
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0, // Reserved
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IntDefaultHandler, // Wide Timer 5 subtimer B
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0, // Reserved
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IntDefaultHandler, // FPU
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IntDefaultHandler, // I2C4 Master and Slave
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0, // Reserved
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IntDefaultHandler, // I2C5 Master and Slave
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0, // Reserved
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IntDefaultHandler, // GPIO Port M
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IntDefaultHandler, // I2C4 Master and Slave
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IntDefaultHandler, // GPIO Port N
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IntDefaultHandler, // I2C5 Master and Slave
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IntDefaultHandler, // Quadrature Encoder 2
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IntDefaultHandler, // GPIO Port M
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0, // Reserved
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IntDefaultHandler, // GPIO Port N
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0, // Reserved
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IntDefaultHandler, // Quadrature Encoder 2
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IntDefaultHandler, // GPIO Port P (Summary or P0)
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0, // Reserved
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IntDefaultHandler, // GPIO Port P1
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0, // Reserved
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IntDefaultHandler, // GPIO Port P2
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IntDefaultHandler, // GPIO Port P (Summary or P0)
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IntDefaultHandler, // GPIO Port P3
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IntDefaultHandler, // GPIO Port P1
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IntDefaultHandler, // GPIO Port P4
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IntDefaultHandler, // GPIO Port P2
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IntDefaultHandler, // GPIO Port P5
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IntDefaultHandler, // GPIO Port P3
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IntDefaultHandler, // GPIO Port P6
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IntDefaultHandler, // GPIO Port P4
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IntDefaultHandler, // GPIO Port P7
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IntDefaultHandler, // GPIO Port P5
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IntDefaultHandler, // GPIO Port Q (Summary or Q0)
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IntDefaultHandler, // GPIO Port P6
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IntDefaultHandler, // GPIO Port Q1
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IntDefaultHandler, // GPIO Port P7
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IntDefaultHandler, // GPIO Port Q2
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IntDefaultHandler, // GPIO Port Q (Summary or Q0)
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IntDefaultHandler, // GPIO Port Q3
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IntDefaultHandler, // GPIO Port Q1
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IntDefaultHandler, // GPIO Port Q4
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IntDefaultHandler, // GPIO Port Q2
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IntDefaultHandler, // GPIO Port Q5
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IntDefaultHandler, // GPIO Port Q3
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IntDefaultHandler, // GPIO Port Q6
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IntDefaultHandler, // GPIO Port Q4
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IntDefaultHandler, // GPIO Port Q7
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IntDefaultHandler, // GPIO Port Q5
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IntDefaultHandler, // GPIO Port R
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IntDefaultHandler, // GPIO Port Q6
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IntDefaultHandler, // GPIO Port S
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IntDefaultHandler, // GPIO Port Q7
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IntDefaultHandler, // PWM 1 Generator 0
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IntDefaultHandler, // GPIO Port R
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IntDefaultHandler, // PWM 1 Generator 1
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IntDefaultHandler, // GPIO Port S
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IntDefaultHandler, // PWM 1 Generator 2
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IntDefaultHandler, // PWM 1 Generator 0
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IntDefaultHandler, // PWM 1 Generator 3
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IntDefaultHandler, // PWM 1 Generator 1
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IntDefaultHandler // PWM 1 Fault
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IntDefaultHandler, // PWM 1 Generator 2
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};
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IntDefaultHandler, // PWM 1 Generator 3
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IntDefaultHandler // PWM 1 Fault
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//*****************************************************************************
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};
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//
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// This is the code that gets called when the processor first starts execution
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//*****************************************************************************
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// following a reset event. Only the absolutely necessary set is performed,
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//
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// after which the application supplied entry() routine is called. Any fancy
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// This is the code that gets called when the processor first starts execution
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// actions (such as making decisions based on the reset cause register, and
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// following a reset event. Only the absolutely necessary set is performed,
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// resetting the bits in that register) are left solely in the hands of the
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// after which the application supplied entry() routine is called. Any fancy
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// application.
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// actions (such as making decisions based on the reset cause register, and
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//
|
// resetting the bits in that register) are left solely in the hands of the
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//*****************************************************************************
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// application.
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void
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//
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ResetISR(void)
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//*****************************************************************************
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{
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void
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//
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ResetISR(void)
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// Jump to the CCS C initialization routine. This will enable the
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{
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// floating-point unit as well, so that does not need to be done here.
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//
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//
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// Jump to the CCS C initialization routine. This will enable the
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__asm(" .global _c_int00\n"
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// floating-point unit as well, so that does not need to be done here.
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" b.w _c_int00");
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//
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}
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__asm(" .global _c_int00\n"
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" b.w _c_int00");
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//*****************************************************************************
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}
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//
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// This is the code that gets called when the processor receives a NMI. This
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//*****************************************************************************
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// simply enters an infinite loop, preserving the system state for examination
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//
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// by a debugger.
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// This is the code that gets called when the processor receives a NMI. This
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//
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// simply enters an infinite loop, preserving the system state for examination
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//*****************************************************************************
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// by a debugger.
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static void
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//
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NmiSR(void)
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//*****************************************************************************
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{
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static void
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//
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NmiSR(void)
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// Enter an infinite loop.
|
{
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//
|
//
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||||||
while(1)
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// Enter an infinite loop.
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{
|
//
|
||||||
}
|
while(1)
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}
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{
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|
}
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//*****************************************************************************
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}
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||||||
//
|
|
||||||
// This is the code that gets called when the processor receives a fault
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//*****************************************************************************
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// interrupt. This simply enters an infinite loop, preserving the system state
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//
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||||||
// for examination by a debugger.
|
// This is the code that gets called when the processor receives a fault
|
||||||
//
|
// interrupt. This simply enters an infinite loop, preserving the system state
|
||||||
//*****************************************************************************
|
// for examination by a debugger.
|
||||||
static void
|
//
|
||||||
FaultISR(void)
|
//*****************************************************************************
|
||||||
{
|
static void
|
||||||
//
|
FaultISR(void)
|
||||||
// Enter an infinite loop.
|
{
|
||||||
//
|
//
|
||||||
while(1)
|
// Enter an infinite loop.
|
||||||
{
|
//
|
||||||
}
|
while(1)
|
||||||
}
|
{
|
||||||
|
}
|
||||||
//*****************************************************************************
|
}
|
||||||
//
|
|
||||||
// This is the code that gets called when the processor receives an unexpected
|
//*****************************************************************************
|
||||||
// interrupt. This simply enters an infinite loop, preserving the system state
|
//
|
||||||
// for examination by a debugger.
|
// This is the code that gets called when the processor receives an unexpected
|
||||||
//
|
// interrupt. This simply enters an infinite loop, preserving the system state
|
||||||
//*****************************************************************************
|
// for examination by a debugger.
|
||||||
static void
|
//
|
||||||
IntDefaultHandler(void)
|
//*****************************************************************************
|
||||||
{
|
static void
|
||||||
//
|
IntDefaultHandler(void)
|
||||||
// Go into an infinite loop.
|
{
|
||||||
//
|
//
|
||||||
while(1)
|
// Go into an infinite loop.
|
||||||
{
|
//
|
||||||
}
|
while(1)
|
||||||
}
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue