From 902418281ca3270cf4e1f71926a0563e318269f9 Mon Sep 17 00:00:00 2001 From: Uttam Ambappa Bhavimani Date: Sun, 22 Sep 2024 19:51:55 +0530 Subject: [PATCH] Update Group21_Lab06_Task2/main.c GPIO_PORT_F Initialization --- Group21_Lab06_Task2/main.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Group21_Lab06_Task2/main.c b/Group21_Lab06_Task2/main.c index bcf15c4..c20d4ce 100644 --- a/Group21_Lab06_Task2/main.c +++ b/Group21_Lab06_Task2/main.c @@ -17,3 +17,17 @@ const long int PWM_PERIOD = 1000000; // Period for 100kHz in microseconds (10ms) #define INTEN (1 << 1) // Bit 1 of CSR to enable interrupt #define SYSTICK_RELOAD_VALUE(us) ((CLOCK_HZ / 1000000) * (us) - 1) // SysTick reload value in microseconds based on clock frequency +void GPIO_PORT_F_init(void) { + SYSCTL_RCGC2_R |= 0x00000020; // Enable clock to GPIOF + GPIO_PORTF_LOCK_R = 0x4C4F434B; // Unlock commit register + GPIO_PORTF_CR_R = 0x1F; // Make PORTF0 configurable + GPIO_PORTF_DEN_R = 0x1F; // Set PORTF digital enable + GPIO_PORTF_DIR_R = 0x0E; // Set PF0, PF4 as input and PF1, PF2, PF3 as output + GPIO_PORTF_PUR_R = 0x11; // PORTF PF0 and PF4 is pulled up + + NVIC_EN0_R |= 1 << 30; // Enable interrupt for PORTF + GPIO_PORTF_IS_R = 0x00; // Make it edge-sensitive + GPIO_PORTF_IBE_R = 0x00; // Trigger on one edge + GPIO_PORTF_IEV_R = 0x00; // Falling edge event + GPIO_PORTF_IM_R |= 0x11; // Unmask interrupts for PF0 and PF4 +}