From c8e45ff5c9515813f26b412e11b2bdb8bfbf5687 Mon Sep 17 00:00:00 2001
From: Vikram Rajput <ee23mt015@iitdh.ac.in>
Date: Tue, 29 Oct 2024 00:51:12 +0530
Subject: [PATCH] UART & Initialization

---
 main.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/main.c b/main.c
index 3f4f1c8..6f2b4be 100644
--- a/main.c
+++ b/main.c
@@ -3,16 +3,61 @@
 #include "tm4c123gh6pm.h"
 
 
-void UART7_Init(void);
-void UART7_Write(char data);
-char UART7_Read(void);
-void PortE_Init(void);
+void UART7_init(void);
+void UART7_write(char data);
+char UART7_read(void);
+void PortE_init(void);
 void LED_Control(char);
 
 
 int main(void)
 {
     char recievedchar;
-    SYSCTL_RCGCUART_R |= 0x80;   // Enable clock to UART7
-    SYSCTL_RCGCGPIO_R |= 0x10;  // Enable port E for uart 7
+
+    UART7_init(); // UART 7 Initialization
+    PortE_Init(); // PORT E Initialization
+
+    while(1)
+        {
+        recievedchar = UART7_read(); // Read a character from the UART
+
+        UART0_Write(receivedChar); // Give the character back to UART
+
+        LED_Control(receivedChar); // LED Control based on UART input
+        }
+
 }
+
+
+void UART7_init(void)
+    {
+    SYSCTL_RCGCUART_R |= 0x80;   // Enable clock to UART7
+    SYSCTL_RCGCGPIO_R |= 0x10  // Enable clock to Port E for UART7
+
+    // UART7 TX/RX on PE1/PE0
+    GPIO_PORTE_AFSEL_R |= 0x03;  // Enable alt function on PE0, PE1
+    GPIO_PORTE_DEN_R |= 0x03;    // Enable digital on PE0, PE1
+    GPIO_PORTE_PCTL_R |= 0x11;   // Configure PE0 and PE1 for UART
+    GPIO_PORTE_AMSEL_R &= ~0x03; // Disable analog on PE0, PE1
+
+
+    // UART7 initialization
+    UART0_CTL_R &= ~0x01;        // Disable UART0
+    UART0_IBRD_R = 104;          // Baud rate = 9600, Integer Baud Rate Divisor
+    UART0_FBRD_R = 11;           // Fractional Baud Rate Divisor
+    UART0_LCRH_R = 0x70;         // 8-bit, no parity, 1-stop bit, enable FIFOs
+    UART0_CTL_R |= 0x301;        // Enable UART0, TX, RX
+
+    }
+
+
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