2024-09-19 22:33:22 +05:30
|
|
|
#include <stdint.h>
|
|
|
|
#include <stdbool.h>
|
|
|
|
#include "tm4c123gh6pm.h"
|
|
|
|
|
|
|
|
#define mask_bits 0x11 //mask bits for user switch
|
2024-09-19 22:40:17 +05:30
|
|
|
|
|
|
|
void GPIOF_config(void);
|
|
|
|
void GPIOF_Int_Config(void);
|
|
|
|
|
|
|
|
void main(void)
|
|
|
|
{
|
|
|
|
SYSCTL_RCC_R &= ~(1 << 20); //SYSTEM CLOCK SOURCE FOR 16MHz PWM
|
|
|
|
SYSCTL_RCGC0_R |= 0x00100000; //enable clock for PWM module
|
|
|
|
SYSCTL_RCGCPWM_R = 0x3; //
|
|
|
|
|
|
|
|
GPIOF_config();
|
2024-09-19 23:07:11 +05:30
|
|
|
GPIOF_Int_Config();
|
2024-09-19 22:40:17 +05:30
|
|
|
GPIO_PORTF_AFSEL_R |= 0x02;
|
|
|
|
GPIO_PORTF_PCTL_R |= 0x50;
|
|
|
|
|
2024-09-19 22:43:43 +05:30
|
|
|
PWM1_2_CTL_R= 0x00000000;
|
2024-09-19 22:40:17 +05:30
|
|
|
|
2024-09-19 22:43:43 +05:30
|
|
|
PWM1_2_GENB_R |= 0x80E;
|
|
|
|
PWM1_2_LOAD_R = 0xA0;
|
2024-09-19 22:40:17 +05:30
|
|
|
|
2024-09-19 22:43:43 +05:30
|
|
|
PWM1_2_CMPB_R = 0x50;
|
|
|
|
PWM1_2_CTL_R |=0x01;
|
|
|
|
PWM1_ENABLE_R |=(1<<5);
|
2024-09-19 22:40:17 +05:30
|
|
|
|
2024-09-19 22:43:43 +05:30
|
|
|
while(1);
|
2024-09-19 22:40:17 +05:30
|
|
|
|
|
|
|
}
|
2024-09-19 22:50:45 +05:30
|
|
|
|
2024-09-19 22:52:40 +05:30
|
|
|
void GPIOF_config()
|
2024-09-19 22:50:45 +05:30
|
|
|
{
|
|
|
|
SYSCTL_RCGC2_R |= 0x20;
|
|
|
|
GPIO_PORTF_LOCK_R = 0x4C4F434B;
|
|
|
|
GPIO_PORTF_CR_R = 0x1F;
|
|
|
|
GPIO_PORTF_DEN_R= 0x1F;
|
|
|
|
GPIO_PORTF_DIR_R= 0x0E;
|
|
|
|
GPIO_PORTF_PUR_R = 0x11;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2024-09-19 22:56:55 +05:30
|
|
|
void GPIOF_Int_Config()
|
|
|
|
{
|
2024-09-19 23:07:11 +05:30
|
|
|
GPIO_PORTF_IM_R &= ~mask_bits;
|
|
|
|
GPIO_PORTF_IS_R &= ~mask_bits;
|
|
|
|
GPIO_PORTF_IEV_R &= ~mask_bits;
|
|
|
|
GPIO_PORTF_IBE_R &= ~mask_bits;
|
2024-09-19 22:56:55 +05:30
|
|
|
NVIC_PRI7_R = (NVIC_PRI7_R & 0xFF1FFFFF) | (2 << 21);
|
|
|
|
NVIC_EN0_R |= (1 << 30);
|
2024-09-19 23:07:11 +05:30
|
|
|
GPIO_PORTF_ICR_R = mask_bits;
|
|
|
|
GPIO_PORTF_IM_R |= mask_bits;
|
2024-09-19 22:50:45 +05:30
|
|
|
|
2024-09-19 22:56:55 +05:30
|
|
|
}
|
2024-09-19 22:50:45 +05:30
|
|
|
|
2024-09-19 23:03:03 +05:30
|
|
|
void GPIOF_INT_Handler(void)
|
|
|
|
{
|
2024-09-19 23:07:11 +05:30
|
|
|
GPIO_PORTF_IM_R &= ~mask_bits;
|
2024-09-19 23:03:03 +05:30
|
|
|
int i;
|
|
|
|
if(GPIO_PORTF_RIS_R & 0x01)
|
|
|
|
{
|
|
|
|
for(i=0;i<160000;i++){}
|
|
|
|
|
|
|
|
if(~(GPIO_PORTF_DATA_R)&0x01)
|
|
|
|
{
|
|
|
|
if(PWM1_2_CMPB_R < 155)
|
|
|
|
{
|
|
|
|
PWM1_2_CMPB_R += 5;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if(GPIO_PORTF_RIS_R & 0x10)
|
|
|
|
{
|
|
|
|
for(i=0;i<160000;i++){}
|
|
|
|
if(~(GPIO_PORTF_DATA_R)&0x10)
|
|
|
|
{
|
|
|
|
if(PWM1_2_CMPB_R > 5)
|
|
|
|
{
|
|
|
|
PWM1_2_CMPB_R -= 5;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2024-09-19 23:07:11 +05:30
|
|
|
GPIO_PORTF_ICR_R = mask_bits;
|
|
|
|
GPIO_PORTF_IM_R |= mask_bits;
|
2024-09-19 22:50:45 +05:30
|
|
|
|
2024-09-19 23:03:03 +05:30
|
|
|
}
|
2024-09-19 22:50:45 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|