Modification
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f11cea27a4
commit
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9
main.c
9
main.c
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@ -36,7 +36,7 @@ int main(void) {
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void PortF_Init(void) {
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void PortF_Init(void) {
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SYSCTL_RCGCGPIO_R |= (1U << 5); // Enable clock for Port F // SYSCTL_RCGC2_R |= 0x00000020;
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SYSCTL_RCGCGPIO_R |= (1U << 5); // Enable clock for Port F // SYSCTL_RCGC2_R |= 0x00000020;
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while ((SYSCTL_PRGPIO_R & (1U << 5)) == 0); // Wait for Port F to be ready
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// while ((SYSCTL_PRGPIO_R & (1U << 5)) == 0); // Wait for Port F to be ready
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GPIO_PORTF_DIR_R |= 0x01; // Set PF1 as output
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GPIO_PORTF_DIR_R |= 0x01; // Set PF1 as output
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GPIO_PORTF_DEN_R |= 0x01; // Enable digital function for PF1
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GPIO_PORTF_DEN_R |= 0x01; // Enable digital function for PF1
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@ -47,7 +47,7 @@ void PortF_Init(void) {
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void ADC0_Init(void) {
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void ADC0_Init(void) {
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SYSCTL_RCGCADC_R |= 0x01; // Enable ADC0 clock
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SYSCTL_RCGCADC_R |= 0x01; // Enable ADC0 clock
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SYSCTL_RCGCGPIO_R |= 0x10; // Enable clock for Port E
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SYSCTL_RCGCGPIO_R |= 0x10; // Enable clock for Port E
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while ((SYSCTL_PRGPIO_R & (1U << 4)) == 0); // Wait for Port E to be ready
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// while ((SYSCTL_PRGPIO_R & (1U << 4)) == 0); // Wait for Port E to be ready
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GPIO_PORTE_AFSEL_R |= (1U << 3); // Enable alternate function on PE3
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GPIO_PORTE_AFSEL_R |= (1U << 3); // Enable alternate function on PE3
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GPIO_PORTE_DEN_R &= ~(1U << 3); // Disable digital I/O on PE3
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GPIO_PORTE_DEN_R &= ~(1U << 3); // Disable digital I/O on PE3
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@ -60,10 +60,11 @@ void ADC0_Init(void) {
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ADC0_ACTSS_R |= 8; // Enable sample sequencer 3
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ADC0_ACTSS_R |= 8; // Enable sample sequencer 3
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}
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}
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uint16_t ADC0_Read(void) {
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uint16_t ADC0_Read(void)
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{
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ADC0_PSSI_R = 8; // Start sampling on SS3
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ADC0_PSSI_R = 8; // Start sampling on SS3
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while ((ADC0_RIS_R & 8) == 0); // Wait for conversion to complete
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while ((ADC0_RIS_R & 8) == 0); // Wait for conversion to complete
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uint16_t result = ADC0_SSFIFO3_R & 0xFFF; // Read 12-bit ADC value
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uint16_t result = ADC0_SSFIFO3_R & 0xFFF; // Read 12-bit ADC value
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ADC0_ISC_R = 8; // Clear the completion flag
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ADC0_ISC_R = 8; // Clear the completion flag
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return result;
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return result;
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}
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}
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