From cf53e1e8e6318abfaaef6055fb1ca0685fb9ccc9 Mon Sep 17 00:00:00 2001 From: Martin Diehl Date: Fri, 17 Apr 2020 11:55:43 +0200 Subject: [PATCH] bugfix: wrong logic for RK and source state --- src/crystallite.f90 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/crystallite.f90 b/src/crystallite.f90 index 1a7ed3e58..a8b2af239 100644 --- a/src/crystallite.f90 +++ b/src/crystallite.f90 @@ -1466,7 +1466,7 @@ subroutine integrateStateRK(todo,A,B,CC,DB) + sourceState(p)%p(s)%dotState (1:sizeDotState,c) & * crystallite_subdt(g,i,e) if(present(DB)) & - broken = broken .and. .not. & + broken = broken .or. .not. & converged(matmul(source_RKdotState(1:sizeDotState,1:size(DB),s),DB) & * crystallite_subdt(g,i,e), & sourceState(p)%p(s)%state(1:sizeDotState,c), &