module Prop1 where
import Clash.Explicit.Testbench
import Clash.Prelude
import ProcessingElement(processingElement)
import Queue(queue,queuetest)
import Queue30(queue30,queuetest30)

queue_mealy1 inp = mealy queue (0:>Nil) inp
queue_mealy2 inp = mealy queue (0:>Nil) inp
queue_mealy3 inp = mealy queue (0:>Nil) inp

processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp

processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp

prop1 (inp1,inp2) = queue_mealy1 (processingElement_mealy_or (bundle ( queue_mealy2 (processingElement_mealy_not (bundle (inp1,inp1))),  
queue_mealy3 (processingElement_mealy_not (bundle (inp2,inp2))) ) ) )

topEntity
  :: Clock System
  -> Reset System
  -> Enable System
  -> (Signal System (Bool), Signal System (Bool))
  -> Signal System ( Bool)
topEntity = exposeClockResetEnable prop1

testBench :: Signal System Bool
testBench = done
  where
    testInput1    = stimuliGenerator clk rst $(listToVecTH [False::Bool , False, True, False, False, True, False, False, True, True, True, True, False])
    testInput2    = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False])
    expectOutput = outputVerifier' clk rst $(listToVecTH [False ::Bool, False, True , True, False, True, True, False, True, True, False, False, False, False, True])
    done         = expectOutput (topEntity clk rst en (testInput1, testInput2))
    en           = enableGen
    clk          = tbSystemClockGen (not <$> done)
    rst          = systemResetGen