module Operators where
import Clash.Explicit.Testbench
import Clash.Prelude
import ProcessingElement(processingElement)
import Queue(queue,queuetest)

f (x,y) = x
g (x,y) = y

queue_mealy1 inp = mealy queue (0:>0:>0:>0:>0:>0:>Nil) inp
queue_mealy2 inp = mealy queuetest (0:>0:>0:>0:>0:>0:>Nil) inp
queue_mealy3 inp = mealy queuetest (0:>Nil) inp

processingElement_mealy_or inp = mealy processingElement (0,(0,0,31,31,31,31,31,31,31,31),(31,31,0,0,31,31,31,31,31,31)) inp
or_out (inp1,inp2) =queue_mealy3 (processingElement_mealy_or (bundle ( inp1,  inp2)))

processingElement_mealy_not inp = mealy processingElement (1,(31,31,0,0,31,31,31,31,31,31),(0,0,31,31,31,31,31,31,31,31)) inp
not_out inp1 =queue_mealy3 (processingElement_mealy_not (bundle ( inp1,  inp1)))

processingElement_mealy_box inp = mealy processingElement (1,(31,31,31,31,0,0,5,5,31,31),(31,31,2,5,0,0,31,31,31,31)) inp
box_out inp1 =queue_mealy2 (processingElement_mealy_box (bundle ( inp1,  inp1)))

processingElement_mealy_diamond inp = mealy processingElement (1,(2,5,31,31,0,0,31,31,31,31),(31,31,31,31,0,0,31,31,5,5)) inp
diamond_out (inp1,inp2) =queue_mealy2 (processingElement_mealy_diamond (bundle ( inp1,  inp2)))

--topEntity
--  :: Clock System
--  -> Reset System
--  -> Enable System
--  -> (Signal System (Bool))
--  -> Signal System (Vec 6 (Signed 2), Bool)
--topEntity = exposeClockResetEnable box_out

--testBench :: Signal System Bool
--testBench = done
--  where
--    testInput1    = stimuliGenerator clk rst $(listToVecTH [True::Bool , False, False, False, False, True, False, False, True, True, True, True, False])
--    testInput2    = stimuliGenerator clk rst $(listToVecTH [True::Bool , True, True, True, True, True, False, False, True, True, True, True, False])
--    expectOutput = outputVerifier' clk rst $(listToVecTH [(0:>0:>0:>0:>0:>0:>Nil,False):: (Vec 6 (Signed 2), Bool), (-1:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,False), (0:>0:>0:>0:>0:>0:>Nil,True),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False),(0:>0:>0:>0:>0:>0:>Nil,False)])
--    done         = expectOutput (topEntity clk rst en (testInput1, testInput2))
--    en           = enableGen
--    clk          = tbSystemClockGen (not <$> done)
--    rst          = systemResetGen