From 783e72c4edb51ef56d5f6f7da16b36f61a29f23f Mon Sep 17 00:00:00 2001 From: karthikmurakonda Date: Fri, 7 Oct 2022 04:29:58 +0530 Subject: [PATCH] even odd.out is working --- assignment-3/bin/configuration/config.xml | 43 +++++++ assignment-3/build.xml | 39 +++++++ assignment-4/src/processor/Processor.java | 2 +- .../pipeline/IF_EnableLatchType.java | 10 ++ .../processor/pipeline/InstructionFetch.java | 33 +++--- .../src/processor/pipeline/OperandFetch.java | 109 ++++++++++++++---- .../src/processor/pipeline/RegisterWrite.java | 16 ++- 7 files changed, 209 insertions(+), 43 deletions(-) create mode 100644 assignment-3/bin/configuration/config.xml create mode 100755 assignment-3/build.xml diff --git a/assignment-3/bin/configuration/config.xml b/assignment-3/bin/configuration/config.xml new file mode 100644 index 0000000..002c97c --- /dev/null +++ b/assignment-3/bin/configuration/config.xml @@ -0,0 +1,43 @@ + + + + + 2 + 1 + 1 + + + 1 + 4 + 1 + + + 1 + 10 + 1 + + + + + 256 + 2 + 4 + LRU + + + + 256 + 2 + 4 + LRU + + + + 2048 + 10 + 4 + LRU + + + 40 + \ No newline at end of file diff --git a/assignment-3/build.xml b/assignment-3/build.xml new file mode 100755 index 0000000..4fb8881 --- /dev/null +++ b/assignment-3/build.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/assignment-4/src/processor/Processor.java b/assignment-4/src/processor/Processor.java index 33e8188..c4a009e 100644 --- a/assignment-4/src/processor/Processor.java +++ b/assignment-4/src/processor/Processor.java @@ -45,7 +45,7 @@ public class Processor { MA_RW_Latch = new MA_RW_LatchType(); IFUnit = new InstructionFetch(this, IF_EnableLatch, IF_OF_Latch, EX_IF_Latch); - OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch); + OFUnit = new OperandFetch(this, IF_OF_Latch, OF_EX_Latch, IF_EnableLatch); EXUnit = new Execute(this, OF_EX_Latch, EX_MA_Latch, EX_IF_Latch); MAUnit = new MemoryAccess(this, EX_MA_Latch, MA_RW_Latch); RWUnit = new RegisterWrite(this, MA_RW_Latch, IF_EnableLatch); diff --git a/assignment-4/src/processor/pipeline/IF_EnableLatchType.java b/assignment-4/src/processor/pipeline/IF_EnableLatchType.java index e0198a5..caf216e 100644 --- a/assignment-4/src/processor/pipeline/IF_EnableLatchType.java +++ b/assignment-4/src/processor/pipeline/IF_EnableLatchType.java @@ -3,10 +3,12 @@ package processor.pipeline; public class IF_EnableLatchType { boolean IF_enable; + boolean freeze; public IF_EnableLatchType() { IF_enable = true; + freeze = false; } public boolean isIF_enable() { @@ -17,4 +19,12 @@ public class IF_EnableLatchType { IF_enable = iF_enable; } + public boolean isFreeze() { + return freeze; + } + + public void setFreeze(boolean freeze) { + this.freeze = freeze; + } + } diff --git a/assignment-4/src/processor/pipeline/InstructionFetch.java b/assignment-4/src/processor/pipeline/InstructionFetch.java index 0e9f955..de31f00 100644 --- a/assignment-4/src/processor/pipeline/InstructionFetch.java +++ b/assignment-4/src/processor/pipeline/InstructionFetch.java @@ -18,21 +18,24 @@ public class InstructionFetch { } public void performIF() - { - if(EX_IF_Latch.isIF_enable()){ - containingProcessor.getRegisterFile().setProgramCounter(EX_IF_Latch.getPC()-1); - EX_IF_Latch.setIF_enable(false); - System.out.println("IF: PC set to " + EX_IF_Latch.getPC()); - } // if EX_IF_Latch is enabled, set PC to EX_IF_Latch's PC and wait for next cycle (1 nop) - else if(IF_EnableLatch.isIF_enable()) - { - int currentPC = containingProcessor.getRegisterFile().getProgramCounter(); - int newInstruction = containingProcessor.getMainMemory().getWord(currentPC); - IF_OF_Latch.setInstruction(newInstruction); - containingProcessor.getRegisterFile().setProgramCounter(currentPC + 1); - - IF_EnableLatch.setIF_enable(true); - IF_OF_Latch.setOF_enable(true); + { if(!IF_EnableLatch.isFreeze()){ + if(EX_IF_Latch.isIF_enable()){ + containingProcessor.getRegisterFile().setProgramCounter(EX_IF_Latch.getPC()-1); + EX_IF_Latch.setIF_enable(false); + System.out.println("IF: PC set to " + EX_IF_Latch.getPC()); + } // if EX_IF_Latch is enabled, set PC to EX_IF_Latch's PC and wait for next cycle (1 nop) + else if(IF_EnableLatch.isIF_enable()) + { + int currentPC = containingProcessor.getRegisterFile().getProgramCounter(); + int newInstruction = containingProcessor.getMainMemory().getWord(currentPC); + IF_OF_Latch.setInstruction(newInstruction); + containingProcessor.getRegisterFile().setProgramCounter(currentPC + 1); + + IF_EnableLatch.setIF_enable(true); + IF_OF_Latch.setOF_enable(true); + } + }else{ + IF_EnableLatch.setFreeze(false); } } diff --git a/assignment-4/src/processor/pipeline/OperandFetch.java b/assignment-4/src/processor/pipeline/OperandFetch.java index 9c3938e..2f49462 100644 --- a/assignment-4/src/processor/pipeline/OperandFetch.java +++ b/assignment-4/src/processor/pipeline/OperandFetch.java @@ -1,6 +1,8 @@ package processor.pipeline; import java.util.Arrays; +import java.util.LinkedList; +import java.util.Queue; import generic.Instruction; import processor.Processor; @@ -12,15 +14,38 @@ public class OperandFetch { Processor containingProcessor; IF_OF_LatchType IF_OF_Latch; OF_EX_LatchType OF_EX_Latch; + IF_EnableLatchType IF_EnableLatch; static OperationType[] opTypes = OperationType.values(); boolean Proceed; + Queue queue; + boolean isEnd; - public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch) + public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch, IF_EnableLatchType iF_EnableLatch) { this.containingProcessor = containingProcessor; this.IF_OF_Latch = iF_OF_Latch; this.OF_EX_Latch = oF_EX_Latch; + this.IF_EnableLatch = iF_EnableLatch; + isEnd = false; Proceed = true; + queue = new LinkedList<>(); + queue.add(-1); + queue.add(-1); + queue.add(-1); + } + + boolean checkdatahazard(int[] operands) { + for(int i=0;i x == opcode)) { Operand rs1 = new Operand(); @@ -100,17 +137,24 @@ public class OperandFetch { } int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue()); int op2 = containingProcessor.getRegisterFile().getValue(rd.getValue()); - System.out.println("imm: " + imm); - - OF_EX_Latch.setInstruction(instr); - OF_EX_Latch.setImm(imm); - OF_EX_Latch.setOp1(op1); - OF_EX_Latch.setOp2(op2); - - System.out.println("op1: " + op1); - System.out.println("op2: " + rd); - instr.setDestinationOperand(rd); - instr.setSourceOperand1(rs1); + // System.out.println("imm: " + imm); + + if (checkdatahazard(new int[] { rs1.getValue() })) { + noDataHazard = false; + }else{ + if(opcode <= 22) { // > 21 means it is a branch instruction so no need to update queue + addtoqueue = rd.getValue(); + } + OF_EX_Latch.setInstruction(instr); + OF_EX_Latch.setImm(imm); + OF_EX_Latch.setOp1(op1); + OF_EX_Latch.setOp2(op2); + instr.setDestinationOperand(rd); + instr.setSourceOperand1(rs1); + } + // if(opcode == 22){ + + // } } else if (Arrays.stream(R1I_type_operators).anyMatch(x -> x == opcode)) { if(opcode != 24){ @@ -125,11 +169,16 @@ public class OperandFetch { imm = -1*twoscompliment(bin_instr.substring(10, 32)); System.out.println(bin_instr); } - System.out.println("imm: " + imm); + // if (checkdatahazard(new int[] { rd.getValue() })) { + // noDataHazard = false; + // }else{ + containingProcessor.getRegisterFile().setProgramCounter(containingProcessor.getRegisterFile().getProgramCounter()-1); OF_EX_Latch.setInstruction(instr); OF_EX_Latch.setImm(imm); + isEnd = true; + // } } - else{ + else{ // opcode == 24 jmp Operand op = new Operand(); String imm = bin_instr.substring(10, 32); int imm_val = Integer.parseInt(imm, 2); @@ -146,16 +195,26 @@ public class OperandFetch { op.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2)); instr.setSourceOperand1(op); } - OF_EX_Latch.setInstruction(instr); - OF_EX_Latch.setImm(imm_val); + if (checkdatahazard(new int[] { op.getValue() })) { + noDataHazard = false; + }else{ + OF_EX_Latch.setInstruction(instr); + OF_EX_Latch.setImm(imm_val); + } } } - OF_EX_Latch.setEX_enable(true); + OF_EX_Latch.setEX_enable(noDataHazard); + if(!noDataHazard){ + IF_EnableLatch.setFreeze(true); + System.out.println("\n\nData Hazard - Interlock\n\n"); + } } else if (!Proceed) { Proceed = true; + System.out.println("\n\nControl Hazard - Interlock\n\n"); } + updateQueue(addtoqueue); } public void setProceed(boolean proceed) { diff --git a/assignment-4/src/processor/pipeline/RegisterWrite.java b/assignment-4/src/processor/pipeline/RegisterWrite.java index bebdf77..783c73e 100644 --- a/assignment-4/src/processor/pipeline/RegisterWrite.java +++ b/assignment-4/src/processor/pipeline/RegisterWrite.java @@ -24,7 +24,7 @@ public class RegisterWrite { Instruction instruction = MA_RW_Latch.getInstruction(); OperationType op_type = instruction.getOperationType(); int alu_result = MA_RW_Latch.getALU_result(); - + boolean proceed = true; if (op_type==OperationType.load) { int load_result = MA_RW_Latch.getLoad_result(); @@ -34,6 +34,7 @@ public class RegisterWrite { else if (op_type==OperationType.end) { Simulator.setSimulationComplete(true); + proceed = false; } else { @@ -44,7 +45,18 @@ public class RegisterWrite { containingProcessor.getRegisterFile().setValue(rd, alu_result); } } - IF_EnableLatch.setIF_enable(true); + IF_EnableLatch.setIF_enable(proceed); + }else{ + try{ + if(MA_RW_Latch.getInstruction().getOperationType() == OperationType.end){ + IF_EnableLatch.setIF_enable(false); + } + else{ + IF_EnableLatch.setIF_enable(true); + } + } catch(Exception e){ + IF_EnableLatch.setIF_enable(true); + } } }