From 2b47f19f2023017f9e80fbfe632bfa5dde812bf8 Mon Sep 17 00:00:00 2001 From: karthikmurakonda Date: Fri, 23 Sep 2022 20:28:34 +0530 Subject: [PATCH] done basic skeleton --- .gitignore | 26 ++++- assignment-3/src/generic/Simulator.java | 37 +++++- assignment-3/src/generic/Statistics.java | 17 ++- .../processor/pipeline/EX_IF_LatchType.java | 19 +++- .../processor/pipeline/EX_MA_LatchType.java | 30 +++++ .../src/processor/pipeline/Execute.java | 107 +++++++++++++++++- .../processor/pipeline/MA_RW_LatchType.java | 31 ++++- .../src/processor/pipeline/MemoryAccess.java | 25 +++- .../processor/pipeline/OF_EX_LatchType.java | 37 ++++++ .../src/processor/pipeline/OperandFetch.java | 80 ++++++++++++- .../src/processor/pipeline/RegisterWrite.java | 29 ++++- 11 files changed, 422 insertions(+), 16 deletions(-) diff --git a/.gitignore b/.gitignore index 6f66c74..f8df812 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,25 @@ -*.zip \ No newline at end of file +*.zip +# Compiled class file +*.class + +# Log file +*.log + +# BlueJ files +*.ctxt + +# Mobile Tools for Java (J2ME) +.mtj.tmp/ + +# Package Files # +*.jar +*.war +*.nar +*.ear +*.zip +*.tar.gz +*.rar + +# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml +hs_err_pid* +replay_pid* diff --git a/assignment-3/src/generic/Simulator.java b/assignment-3/src/generic/Simulator.java index d093f82..2accba4 100644 --- a/assignment-3/src/generic/Simulator.java +++ b/assignment-3/src/generic/Simulator.java @@ -1,5 +1,8 @@ package generic; +import java.io.FileInputStream; +import java.io.InputStream; + import processor.Clock; import processor.Processor; @@ -19,7 +22,6 @@ public class Simulator { static void loadProgram(String assemblyProgramFile) { /* - * TODO * 1. load the program into memory according to the program layout described * in the ISA specification * 2. set PC to the address of the first instruction in the main @@ -28,6 +30,37 @@ public class Simulator { * x1 = 65535 * x2 = 65535 */ + + try ( + InputStream is = new FileInputStream(assemblyProgramFile); + ){ + int i = 0; + byte[] line = new byte[4]; + boolean isFirstLine = true; + while(is.read(line) != -1) { + int value = 0; + for(int j = 0; j < 4; j++) { + value = (value << 8) | (line[j] & 0xff); + } + System.out.println(value); + if(isFirstLine) { + processor.getRegisterFile().setProgramCounter(value); + isFirstLine = false; + }else{ + processor.getMainMemory().setWord(i, value); + i++; + } + } + processor.getRegisterFile().setValue(0, 0); + processor.getRegisterFile().setValue(1, 65535); + processor.getRegisterFile().setValue(2, 65535); + + // Debug + System.out.println(processor.getRegisterFile().getProgramCounter()); + System.out.println(processor.getMainMemory().getContentsAsString(0, 10)); + } catch (Exception e) { + e.printStackTrace(); + } } public static void simulate() @@ -44,6 +77,8 @@ public class Simulator { Clock.incrementClock(); processor.getRWUnit().performRW(); Clock.incrementClock(); + Statistics.setNumberOfInstructions(Statistics.getNumberOfInstructions() + 1); + Statistics.setNumberOfCycles(Statistics.getNumberOfCycles() + 1); } // TODO diff --git a/assignment-3/src/generic/Statistics.java b/assignment-3/src/generic/Statistics.java index 20125e6..a595d0b 100644 --- a/assignment-3/src/generic/Statistics.java +++ b/assignment-3/src/generic/Statistics.java @@ -27,13 +27,22 @@ public class Statistics { Misc.printErrorAndExit(e.getMessage()); } } - // TODO write functions to update statistics - public void setNumberOfInstructions(int numberOfInstructions) { + + public static int getNumberOfInstructions() + { + return numberOfInstructions; + } + public static int getNumberOfCycles() + { + return numberOfCycles; + } + public static void setNumberOfInstructions(int numberOfInstructions) + { Statistics.numberOfInstructions = numberOfInstructions; } - - public void setNumberOfCycles(int numberOfCycles) { + public static void setNumberOfCycles(int numberOfCycles) { Statistics.numberOfCycles = numberOfCycles; } + } diff --git a/assignment-3/src/processor/pipeline/EX_IF_LatchType.java b/assignment-3/src/processor/pipeline/EX_IF_LatchType.java index 6ca9646..cc4d1a6 100644 --- a/assignment-3/src/processor/pipeline/EX_IF_LatchType.java +++ b/assignment-3/src/processor/pipeline/EX_IF_LatchType.java @@ -1,10 +1,27 @@ package processor.pipeline; public class EX_IF_LatchType { + int pc; + boolean IF_enable; public EX_IF_LatchType() { - + IF_enable = false; } + public boolean isIF_enable() { + return IF_enable; + } + + public void setIF_enable(boolean iF_enable) { + IF_enable = iF_enable; + } + + public int getPC() { + return pc; + } + + public void setPC(int pc) { + this.pc = pc; + } } diff --git a/assignment-3/src/processor/pipeline/EX_MA_LatchType.java b/assignment-3/src/processor/pipeline/EX_MA_LatchType.java index cf74f38..06ba930 100644 --- a/assignment-3/src/processor/pipeline/EX_MA_LatchType.java +++ b/assignment-3/src/processor/pipeline/EX_MA_LatchType.java @@ -1,14 +1,44 @@ package processor.pipeline; +import generic.Instruction; +import generic.Operand; + public class EX_MA_LatchType { boolean MA_enable; + Operand op2; + Instruction instruction; + int aluResult; public EX_MA_LatchType() { MA_enable = false; } + public void setInstruction(Instruction instruction) { + this.instruction = instruction; + } + + public Instruction getInstruction() { + return instruction; + } + + public void setOp2(Operand op2) { + this.op2 = op2; + } + + public Operand getOp2(){ + return op2; + } + + public void setALUResult(int aluResult) { + this.aluResult = aluResult; + } + + public int getALUResult(){ + return aluResult; + } + public boolean isMA_enable() { return MA_enable; } diff --git a/assignment-3/src/processor/pipeline/Execute.java b/assignment-3/src/processor/pipeline/Execute.java index df6e251..e70cdde 100644 --- a/assignment-3/src/processor/pipeline/Execute.java +++ b/assignment-3/src/processor/pipeline/Execute.java @@ -1,6 +1,9 @@ package processor.pipeline; - import processor.Processor; +import generic.Instruction; +import generic.Instruction.OperationType; +import generic.Simulator; +import generic.Operand.OperandType; public class Execute { Processor containingProcessor; @@ -19,6 +22,106 @@ public class Execute { public void performEX() { //TODO + if(OF_EX_Latch.isEX_enable()) + { + int op1 = OF_EX_Latch.getOp1(); + int op2 = OF_EX_Latch.getOp2(); + int imm = OF_EX_Latch.getImm(); + Instruction instruction = OF_EX_Latch.getInstruction(); + int cur_pc = containingProcessor.getRegisterFile().getProgramCounter(); + int alu_result = 0; + OperationType alu_op = OF_EX_Latch.getInstruction().getOperationType(); + switch(alu_op) + { + case add: alu_result = op1 + op2; break; + case addi: alu_result = op1 + imm; break; + case sub: alu_result = op1 - op2; break; + case subi: alu_result = op1 - imm; break; + case mul: alu_result = op1 * op2; break; + case muli: alu_result = op1 * imm; break; + case div: alu_result = op1 / op2; break; + case divi: alu_result = op1 / imm; break; + case and: alu_result = op1 & op2; break; + case andi: alu_result = op1 & imm; break; + case or: alu_result = op1 | op2; break; + case ori: alu_result = op1 | imm; break; + case xor: alu_result = op1 ^ op2; break; + case xori: alu_result = op1 ^ imm; break; + case slt: alu_result= (op1 < op2) ? 1 : 0; break; + case slti: alu_result= (op1 < imm) ? 1 : 0; break; + case sll: alu_result = op1 << op2; break; + case slli: alu_result = op1 << imm; break; + case srl: alu_result = op1 >>> op2; break; + case srli: alu_result = op1 >>> imm; break; + case sra: alu_result = op1 >> op2; break; + case srai: alu_result = op1 >> imm; break; + case jmp: + { + OperandType optype = instruction.getDestinationOperand().getOperandType(); + if (optype == OperandType.Register){ + imm = containingProcessor.getRegisterFile().getValue( + instruction.getDestinationOperand().getValue()); + } + else{ + imm = OF_EX_Latch.getImm(); + } + alu_result = cur_pc + imm; + EX_IF_Latch.setIF_enable(true); + EX_IF_Latch.setPC(alu_result); + } + break; + case beq: + { + if(op1 == op2) + { + alu_result = cur_pc + imm; + EX_IF_Latch.setIF_enable(true); + EX_IF_Latch.setPC(alu_result); + } + } + break; + case bne: + { + if(op1 != op2) + { + alu_result = cur_pc + imm; + EX_IF_Latch.setIF_enable(true); + EX_IF_Latch.setPC(alu_result); + } + } + break; + case blt: + { + if(op1 < op2) + { + alu_result = cur_pc + imm; + EX_IF_Latch.setIF_enable(true); + EX_IF_Latch.setPC(alu_result); + } + } + break; + case bgt: + { + if(op1 > op2) + { + alu_result = cur_pc + imm; + EX_IF_Latch.setIF_enable(true); + EX_IF_Latch.setPC(alu_result); + } + } + break; + case end: + { + Simulator.setSimulationComplete(true); + } + default: + break; + + } + EX_MA_Latch.setALUResult(alu_result); + EX_MA_Latch.setInstruction(OF_EX_Latch.getInstruction()); + EX_MA_Latch.setMA_enable(true); + OF_EX_Latch.setEX_enable(false); + } } - } diff --git a/assignment-3/src/processor/pipeline/MA_RW_LatchType.java b/assignment-3/src/processor/pipeline/MA_RW_LatchType.java index 7e9f76a..8d7d0b7 100644 --- a/assignment-3/src/processor/pipeline/MA_RW_LatchType.java +++ b/assignment-3/src/processor/pipeline/MA_RW_LatchType.java @@ -1,12 +1,18 @@ package processor.pipeline; +import generic.Instruction; + public class MA_RW_LatchType { boolean RW_enable; - + int aluResult; + int load_result; + Instruction instruction; + public MA_RW_LatchType() { RW_enable = false; + } public boolean isRW_enable() { @@ -17,4 +23,27 @@ public class MA_RW_LatchType { RW_enable = rW_enable; } + public void setALU_result(int alu_result) { + this.aluResult = alu_result; + } + + public int getALU_result() { + return aluResult; + } + + public void setLoad_result(int load_result) { + this.load_result = load_result; + } + + public int getLoad_result() { + return load_result; + } + + public void setInstruction(Instruction instruction) { + this.instruction = instruction; + } + + public Instruction getInstruction() { + return instruction; + } } diff --git a/assignment-3/src/processor/pipeline/MemoryAccess.java b/assignment-3/src/processor/pipeline/MemoryAccess.java index 1f1684c..30f4aab 100644 --- a/assignment-3/src/processor/pipeline/MemoryAccess.java +++ b/assignment-3/src/processor/pipeline/MemoryAccess.java @@ -1,6 +1,8 @@ package processor.pipeline; +import generic.Instruction; import processor.Processor; +import generic.Instruction.OperationType; public class MemoryAccess { Processor containingProcessor; @@ -16,7 +18,28 @@ public class MemoryAccess { public void performMA() { - //TODO + if(EX_MA_Latch.isMA_enable()) + { + Instruction instruction = EX_MA_Latch.getInstruction(); + int alu_result = EX_MA_Latch.getALUResult(); + MA_RW_Latch.setALU_result(alu_result); + OperationType op_type = instruction.getOperationType(); + if (op_type==OperationType.store) + { + int val_store = containingProcessor.getRegisterFile().getValue( + instruction.getSourceOperand1().getValue()); + containingProcessor.getMainMemory().setWord(alu_result, val_store); + } + else if (op_type==OperationType.load) + { + int load_result = containingProcessor.getMainMemory().getWord(alu_result); + MA_RW_Latch.setLoad_result(load_result); + } + MA_RW_Latch.setInstruction(instruction); + MA_RW_Latch.setRW_enable(true); + EX_MA_Latch.setMA_enable(false); + + } } } diff --git a/assignment-3/src/processor/pipeline/OF_EX_LatchType.java b/assignment-3/src/processor/pipeline/OF_EX_LatchType.java index 0339fae..5ea4e4b 100644 --- a/assignment-3/src/processor/pipeline/OF_EX_LatchType.java +++ b/assignment-3/src/processor/pipeline/OF_EX_LatchType.java @@ -1,14 +1,50 @@ package processor.pipeline; +import generic.Instruction; + public class OF_EX_LatchType { boolean EX_enable; + Instruction instruction; + int op1, op2, imm; public OF_EX_LatchType() { EX_enable = false; } + public void setInstruction(Instruction instruction) { + this.instruction = instruction; + } + + public Instruction getInstruction() { + return instruction; + } + + public void setOp1(int op1) { + this.op1 = op1; + } + + public int getOp1() { + return op1; + } + + public void setOp2(int op2) { + this.op2 = op2; + } + + public int getOp2() { + return op2; + } + + public void setImm(int imm) { + this.imm = imm; + } + + public int getImm() { + return imm; + } + public boolean isEX_enable() { return EX_enable; } @@ -17,4 +53,5 @@ public class OF_EX_LatchType { EX_enable = eX_enable; } + } diff --git a/assignment-3/src/processor/pipeline/OperandFetch.java b/assignment-3/src/processor/pipeline/OperandFetch.java index 9620261..2b9309a 100644 --- a/assignment-3/src/processor/pipeline/OperandFetch.java +++ b/assignment-3/src/processor/pipeline/OperandFetch.java @@ -1,11 +1,17 @@ package processor.pipeline; +import java.util.Arrays; + +import generic.Instruction; import processor.Processor; +import generic.Instruction.OperationType; +import generic.Operand; public class OperandFetch { Processor containingProcessor; IF_OF_LatchType IF_OF_Latch; OF_EX_LatchType OF_EX_Latch; + static OperationType[] opTypes = OperationType.values(); public OperandFetch(Processor containingProcessor, IF_OF_LatchType iF_OF_Latch, OF_EX_LatchType oF_EX_Latch) { @@ -18,8 +24,80 @@ public class OperandFetch { { if(IF_OF_Latch.isOF_enable()) { - //TODO + int instruction = IF_OF_Latch.getInstruction(); + Instruction instr = new Instruction(); + String bin_instr = Integer.toBinaryString(instruction); + int opcode = Integer.parseInt(bin_instr.substring(0, 5), 2); + instr.setOperationType(opTypes[opcode]); + int R3_type_operators[] = {0,2,4,6,8,10,12,14,16,18,20}; + int R2I_type_operators[] = {1,3,5,7,9,11,13,15,17,19,21,22,23,25,26,27,28}; + int R1I_type_operators[] = {24,29}; + + // if (bin_instr.length() < 32) { // TODO: check if this is correct + // int diff = 32 - bin_instr.length(); + // String zeros = ""; + // for (int i = 0; i < diff; i++) { + // zeros += "0"; + // } + // bin_instr = zeros + bin_instr; + // } + + if (Arrays.asList(R3_type_operators).contains(opcode)){ + Operand rs1 = new Operand(); + Operand rs2 = new Operand(); + Operand rd = new Operand(); + rs1.setOperandType(Operand.OperandType.Register); + rs2.setOperandType(Operand.OperandType.Register); + rd.setOperandType(Operand.OperandType.Register); + + rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2)); + rs2.setValue(Integer.parseInt(bin_instr.substring(9, 14), 2)); + rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2)); + + int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue()); + int op2 = containingProcessor.getRegisterFile().getValue(rs2.getValue()); + + OF_EX_Latch.setInstruction(instr); + OF_EX_Latch.setOp1(op1); + OF_EX_Latch.setOp2(op2); + instr.setDestinationOperand(rd); + instr.setSourceOperand1(rs1); + instr.setSourceOperand2(rs2); + } + else if (Arrays.asList(R2I_type_operators).contains(opcode)){ + Operand rs1 = new Operand(); + Operand rd = new Operand(); + rs1.setOperandType(Operand.OperandType.Register); + rd.setOperandType(Operand.OperandType.Register); + + rs1.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2)); + rd.setValue(Integer.parseInt(bin_instr.substring(14, 19), 2)); + + int imm = Integer.parseInt(bin_instr.substring(19, 32), 2); // TODO: 2's complement + + int op1 = containingProcessor.getRegisterFile().getValue(rs1.getValue()); + + OF_EX_Latch.setInstruction(instr); + OF_EX_Latch.setImm(imm); + OF_EX_Latch.setOp1(op1); + + instr.setDestinationOperand(rd); + instr.setSourceOperand1(rs1); + } + else if (Arrays.asList(R1I_type_operators).contains(opcode)){ + Operand rd = new Operand(); + rd.setOperandType(Operand.OperandType.Register); + rd.setValue(Integer.parseInt(bin_instr.substring(5, 10), 2)); + + instr.setDestinationOperand(rd); + + int imm = Integer.parseInt(bin_instr.substring(10, 32), 2); // TODO: 2's complement + + OF_EX_Latch.setInstruction(instr); + OF_EX_Latch.setImm(imm); + } + IF_OF_Latch.setOF_enable(false); OF_EX_Latch.setEX_enable(true); } diff --git a/assignment-3/src/processor/pipeline/RegisterWrite.java b/assignment-3/src/processor/pipeline/RegisterWrite.java index 21cba98..71d9fc4 100644 --- a/assignment-3/src/processor/pipeline/RegisterWrite.java +++ b/assignment-3/src/processor/pipeline/RegisterWrite.java @@ -2,6 +2,8 @@ package processor.pipeline; import generic.Simulator; import processor.Processor; +import generic.Instruction; +import generic.Instruction.OperationType; public class RegisterWrite { Processor containingProcessor; @@ -19,10 +21,29 @@ public class RegisterWrite { { if(MA_RW_Latch.isRW_enable()) { - //TODO - - // if instruction being processed is an end instruction, remember to call Simulator.setSimulationComplete(true); - + Instruction instruction = MA_RW_Latch.getInstruction(); + OperationType op_type = instruction.getOperationType(); + int alu_result = MA_RW_Latch.getALU_result(); + + if (op_type==OperationType.load) + { + int load_result = MA_RW_Latch.getLoad_result(); + int rd = instruction.getDestinationOperand().getValue(); + containingProcessor.getRegisterFile().setValue(rd, load_result); + } + else if (op_type==OperationType.end) + { + Simulator.setSimulationComplete(true); + } + else + { + if (op_type!=OperationType.store && op_type!= OperationType.jmp && op_type!= OperationType.beq && op_type!=OperationType.bne && op_type!=OperationType.blt && op_type!=OperationType.bgt) + { + int rd = instruction.getDestinationOperand().getValue(); + rd = instruction.getDestinationOperand().getValue(); + containingProcessor.getRegisterFile().setValue(rd, alu_result); + } + } MA_RW_Latch.setRW_enable(false); IF_EnableLatch.setIF_enable(true); }