39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
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#ifndef _KERN_SERIAL_H
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#define _KERN_SERIAL_H 1
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#define THRREG 0 /* transmitter holding, write-only, DLAB must be clear */
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#define RBRREG 0 /* receiver buffer, read-only, DLAB must be clear */
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#define DLLREG 0 /* divisor latch LSB, read/write, DLAB must be set */
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#define DLMREG 1 /* divisor latch MSB, read/write, DLAB must be set */
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#define FICRREG 2 /* FIFO control, write-only */
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#define LCRREG 3 /* line control, read/write */
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#define LSRREG 5 /* line status, read-only */
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#define SPRREG 7
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#define COM1_BASE 0x3F8
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#define COM1_THR (COM1_BASE + THRREG)
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#define COM1_RBR (COM1_BASE + RBRREG)
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#define COM1_DLL (COM1_BASE + DLLREG)
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#define COM1_DLM (COM1_BASE + DLMREG)
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#define COM1_LCR (COM1_BASE + LCRREG)
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#define LCR_5BIT 0x00 /* 5 bits per data word */
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#define LCR_6BIT 0x01 /* 6 bits per data word */
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#define LCR_7BIT 0x02 /* 7 bits per data word */
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#define LCR_8BIT 0x03 /* 8 bits per data word */
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#define LCR_1STOP 0x00 /* 1/1.5 stop bits */
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#define LCR_2STOP 0x04 /* 2 stop bits */
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#define LCR_NPAR 0x00 /* no parity */
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#define LCR_OPAR 0x08 /* odd parity */
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#define LCR_EPAR 0x18 /* even parity */
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#define LCR_BREAK 0x40 /* enable break */
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#define LCR_DLAB 0x80 /* access DLAB registers */
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#define COM1_LSR (COM1_BASE + LSRREG)
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#define LSR_DR 0x01
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#define LSR_THRE 0x20
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#define LCR_DLA 0x80
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#define UART_BASE_FREQ 115200U
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#endif
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