175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
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/**
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* @file e1000.h
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*
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* @brief Hardware specific datastructures of the Intel
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* Pro/1000 Gigabit Ethernet card(s).
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*
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* Parts of this code is based on the DragonflyBSD (FreeBSD)
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* implementation, and the fxp driver for Minix 3.
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*
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* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
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* @see fxp.c
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*
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* @author Niek Linnenbank <nieklinnenbank@gmail.com>
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* @date September 2009
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*
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*/
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#ifndef __E1000_HW_H
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#define __E1000_HW_H
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#include <stdint.h>
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/**
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* @name Datastructures.
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* @{
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*/
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/**
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* @brief Receive Descriptor Format.
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*/
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typedef struct e1000_rx_desc
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{
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u32_t buffer; /**< Address of the receive data buffer (64-bit). */
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u32_t buffer_h; /**< High 32-bits of the receive data buffer (unused). */
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u16_t length; /**< Size of the receive buffer. */
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u16_t checksum; /**< Packet checksum. */
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u8_t status; /**< Descriptor status. */
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u8_t errors; /**< Descriptor errors. */
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u16_t special; /**< VLAN information. */
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}
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e1000_rx_desc_t;
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/**
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* @brief Transmit Descriptor Format.
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*/
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typedef struct e1000_tx_desc
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{
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u32_t buffer; /**< Address of the transmit buffer (64-bit). */
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u32_t buffer_h; /**< High 32-bits of the transmit buffer (unused). */
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u16_t length; /**< Size of the transmit buffer contents. */
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u8_t checksum_off; /**< Checksum Offset. */
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u8_t command; /**< Command field. */
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u8_t status; /**< Status field. */
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u8_t checksum_st; /**< Checksum Start. */
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u16_t special; /**< Optional special bits. */
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}
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e1000_tx_desc_t;
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/**
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* @brief ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown.
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* @see http://gitweb.dragonflybsd.org
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*/
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union ich8_hws_flash_status
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{
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struct ich8_hsfsts
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{
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unsigned flcdone :1; /**< bit 0 Flash Cycle Done */
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unsigned flcerr :1; /**< bit 1 Flash Cycle Error */
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unsigned dael :1; /**< bit 2 Direct Access error Log */
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unsigned berasesz :2; /**< bit 4:3 Sector Erase Size */
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unsigned flcinprog :1; /**< bit 5 flash cycle in Progress */
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unsigned reserved1 :2; /**< bit 13:6 Reserved */
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unsigned reserved2 :6; /**< bit 13:6 Reserved */
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unsigned fldesvalid :1; /**< bit 14 Flash Descriptor Valid */
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unsigned flockdn :1; /**< bit 15 Flash Config Lock-Down */
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} hsf_status;
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u16_t regval;
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};
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/**
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* @brief ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown.
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* @see http://gitweb.dragonflybsd.org
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*/
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union ich8_hws_flash_ctrl
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{
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struct ich8_hsflctl
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{
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unsigned flcgo :1; /**< 0 Flash Cycle Go */
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unsigned flcycle :2; /**< 2:1 Flash Cycle */
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unsigned reserved :5; /**< 7:3 Reserved */
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unsigned fldbcount :2; /**< 9:8 Flash Data Byte Count */
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unsigned flockdn :6; /**< 15:10 Reserved */
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} hsf_ctrl;
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u16_t regval;
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};
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/**
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* @brief ICH Flash Region Access Permissions.
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* @see http://gitweb.dragonflybsd.org
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*/
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union ich8_hws_flash_regacc
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{
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struct ich8_flracc
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{
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unsigned grra :8; /**< 0:7 GbE region Read Access */
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unsigned grwa :8; /**< 8:15 GbE region Write Access */
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unsigned gmrag :8; /**< 23:16 GbE Master Read Access Grant */
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unsigned gmwag :8; /**< 31:24 GbE Master Write Access Grant */
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} hsf_flregacc;
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u16_t regval;
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};
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/**
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* @}
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*/
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/**
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* @name Receive Status Field Bits.
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* @{
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*/
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/** Passed In-exact Filter. */
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#define E1000_RX_STATUS_PIF (1 << 7)
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/** End of Packet. */
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#define E1000_RX_STATUS_EOP (1 << 1)
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/** Descriptor Done. */
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#define E1000_RX_STATUS_DONE (1 << 0)
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/**
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* @}
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*/
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/**
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* @name Receive Errors Field Bits.
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* @{
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*/
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/** RX Data Error. */
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#define E1000_RX_ERROR_RXE (1 << 7)
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/** Carrier Extension Error. */
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#define E1000_RX_ERROR_CXE (1 << 4)
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/** Sequence/Framing Error. */
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#define E1000_RX_ERROR_SEQ (1 << 2)
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/** CRC/Alignment Error. */
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#define E1000_RX_ERROR_CE (1 << 0)
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/**
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* @}
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*/
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/**
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* @name Transmit Command Field Bits.
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* @{
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*/
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/** End of Packet. */
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#define E1000_TX_CMD_EOP (1 << 0)
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/** Insert FCS/CRC. */
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#define E1000_TX_CMD_FCS (1 << 1)
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/** Report Status. */
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#define E1000_TX_CMD_RS (1 << 3)
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/**
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* @}
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*/
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#endif /* __E1000_HW_H */
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