163 lines
6.1 KiB
C
163 lines
6.1 KiB
C
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/*
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** File: 3c509.h Jun. 01, 2000
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**
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** Author: Giovanni Falzoni <gfalzoni@inwind.it>
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**
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** Interface description for 3Com Etherlink III board.
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**
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** $Log$
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** Revision 1.1 2005/06/29 10:16:46 beng
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** Import of dpeth 3c501/3c509b/.. ethernet driver by
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** Giovanni Falzoni <fgalzoni@inwind.it>.
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**
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** Revision 2.0 2005/06/26 16:16:46 lsodgf0
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** Initial revision for Minix 3.0.6
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*/
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/* Command codes */
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#define CMD_GlobalReset 0x0000 /* resets adapter (power up status) */
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#define CMD_SelectWindow (1<<11) /* select register window */
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#define CMD_StartIntXcvr (2<<11) /* start internal transciver */
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#define CMD_RxDisable (3<<11) /* rx disable */
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#define CMD_RxEnable (4<<11) /* rx enable */
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#define CMD_RxReset (5<<11) /* rx reset */
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#define CMD_RxDiscard (8<<11) /* rx discard top packet */
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#define CMD_TxEnable (9<<11) /* tx enable */
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#define CMD_TxDisable (10<<11) /* tx disable */
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#define CMD_TxReset (11<<11) /* tx reset */
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#define CMD_Acknowledge (13<<11) /* acknowledge interrupt */
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#define CMD_SetIntMask (14<<11) /* set interrupt mask */
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#define CMD_SetStatusEnab (15<<11) /* set read zero mask */
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#define CMD_SetRxFilter (16<<11) /* set rx filter */
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#define CMD_SetTxAvailable (18<<11) /* set tx available threshold */
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#define CMD_StatsEnable (21<<11) /* statistics enable */
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#define CMD_StatsDisable (22<<11) /* statistics disable */
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#define CMD_StopIntXcvr (23<<11) /* start internal transciver */
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/* Status register bits (INT for interrupt sources, ST for the rest) */
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#define INT_Latch 0x0001 /* interrupt latch */
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#define INT_AdapterFail 0x0002 /* adapter failure */
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#define INT_TxComplete 0x0004 /* tx complete */
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#define INT_TxAvailable 0x0008 /* tx available */
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#define INT_RxComplete 0x0010 /* rx complete */
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#define INT_RxEarly 0x0020 /* rx early */
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#define INT_Requested 0x0040 /* interrupt requested */
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#define INT_UpdateStats 0x0080 /* update statistics */
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/* Rx Status register bits */
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#define RXS_Error 0x4000 /* error in packet */
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#define RXS_Length 0x07FF /* bytes in RxFIFO */
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#define RXS_ErrType 0x3800 /* Rx error type, bit 13-11 */
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#define RXS_Overrun 0x0000 /* overrun error */
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#define RXS_Oversize 0x0800 /* oversize packet error */
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#define RXS_Dribble 0x1000 /* dribble bit (not an error) */
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#define RXS_Runt 0x1800 /* runt packet error */
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#define RXS_Framing 0x2000 /* framing error */
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#define RXS_CRC 0x2800 /* CRC error */
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/* Tx Status register bits */
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/* Window Numbers */
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#define WNO_Setup 0x0000 /* setup/configuration */
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#define WNO_Operating 0x0001 /* operating set */
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#define WNO_StationAddress 0x0002 /* station address setup/read */
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#define WNO_Diagnostics 0x0004 /* diagnostics */
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#define WNO_Statistics 0x0006 /* statistics */
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/* Register offsets - Window 1 (WNO_Operating) */
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#define REG_CmdStatus 0x000E /* command/status */
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#define REG_TxFree 0x000C /* free transmit bytes */
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#define REG_TxStatus 0x000B /* transmit status (byte) */
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#define REG_RxStatus 0x0008 /* receive status */
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#define REG_RxFIFO 0x0000 /* RxFIFO read */
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#define REG_TxFIFO 0x0000 /* TxFIFO write */
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/* Register offsets - Window 0 (WNO_Setup) */
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#define REG_CfgControl 0x0004 /* configuration control */
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/* Register offsets - Window 2 (WNO_StationAddress) */
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#define REG_SA0_1 0x0000 /* station address bytes 0,1 */
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/* Register offsets - Window 3 (WNO_FIFO) */
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/* Register offsets - Window 4 (WNO_Diagnostics) */
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#define REG_MediaStatus 0x000A /* media type/status */
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/* Register offsets - Window 5 (WNO_Readable) */
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/* Register offsets - Window 6 (WNO_Statistics) */
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#define REG_TxBytes 0x000C /* tx bytes ok */
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#define REG_RxBytes 0x000A /* rx bytes ok */
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#define REG_TxDefer 0x0008 /* tx frames deferred (byte) */
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#define REG_RxFrames 0x0007 /* rx frames ok (byte) */
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#define REG_TxFrames 0x0006 /* tx frames ok (byte) */
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#define REG_RxDiscarded 0x0005 /* rx frames discarded (byte) */
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#define REG_TxLate 0x0004 /* tx frames late coll. (byte) */
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#define REG_TxSingleColl 0x0003 /* tx frames one coll. (byte) */
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#define REG_TxMultColl 0x0002 /* tx frames mult. coll. (byte) */
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#define REG_TxNoCD 0x0001 /* tx frames no CDheartbt (byte) */
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#define REG_TxCarrierLost 0x0000 /* tx frames carrier lost (byte) */
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/* Various command arguments */
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#define FilterIndividual 0x0001 /* individual address */
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#define FilterMulticast 0x0002 /* multicast/group addresses */
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#define FilterBroadcast 0x0004 /* broadcast address */
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#define FilterPromiscuous 0x0008 /* promiscuous mode */
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/* Resource Configuration Register bits */
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#define EL3_CONFIG_IRQ_MASK 0xF000
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/* Address Configuration Register bits */
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#define EL3_CONFIG_XCVR_MASK 0xC000
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#define EL3_CONFIG_IOBASE_MASK 0x001F
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#define TP_XCVR 0x0000
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#define BNC_XCVR 0xC000
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#define AUI_XCVR 0x4000
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#define EL3_IO_BASE_ADDR 0x200
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/* Transmit Preamble */
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/* Bits in various diagnostics registers */
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#define MediaLBeatEnable 0x0080 /* link beat enable (TP) */
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#define MediaJabberEnable 0x0040 /* jabber enable (TP) */
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/* Board identification codes, byte swapped in Rev 0 */
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#define EL3_3COM_CODE 0x6D50 /* EISA manufacturer code */
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#define EL3_PRODUCT_ID 0x9050 /* Product ID for ISA board */
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/* EEProm access */
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#define EE_3COM_NODE_ADDR 0x00
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#define EE_PROD_ID 0x03
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#define EE_MANUFACTURING_DATA 0x04
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#define EE_3COM_CODE 0x07
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#define EE_ADDR_CFG 0x08
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#define EE_RESOURCE_CFG 0x09
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#define EE_SW_CONFIG_INFO 0x0D
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#define EE_PROD_ID_MASK 0xF0FF /* Mask off revision nibble */
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/* Contention logic */
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#define EL3_READ_EEPROM 0x80
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#define EL3_ID_GLOBAL_RESET 0xC0
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#define EL3_SET_TAG_REGISTER 0xD0
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#define EL3_ACTIVATE_AND_SET_IO 0xE0
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#define EL3_ACTIVATE 0xFF
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/* Software Configuration Register bits */
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/* Configuration Control Register bits */
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#define EL3_EnableAdapter 0x01
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/* EL3 access macros */
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#define inb_el3(dep,reg) (inb((dep)->de_base_port+(reg)))
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#define inw_el3(dep,reg) (inw((dep)->de_base_port+(reg)))
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#define outb_el3(dep,reg,data) (outb((dep)->de_base_port+(reg),(data)))
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#define outw_el3(dep,reg,data) (outw((dep)->de_base_port+(reg),(data)))
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#define SetWindow(win) \
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outw(dep->de_base_port+REG_CmdStatus,CMD_SelectWindow|(win))
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/** 3c509.h **/
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