241 lines
6.5 KiB
C
241 lines
6.5 KiB
C
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#include "sample_rate_converter.h"
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#define SRC_RATE 48000U
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#define reg(n) DSP->base + n
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/* register/base and control equates for the SRC RAM */
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#define SRC_SYNTH_FIFO 0x00
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#define SRC_DAC_FIFO 0x20
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#define SRC_ADC_FIFO 0x40
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#define SRC_SYNTH_LVOL 0x7c
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#define SRC_SYNTH_RVOL 0x7d
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#define SRC_DAC_LVOL 0x7e
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#define SRC_DAC_RVOL 0x7f
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#define SRC_ADC_LVOL 0x6c
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#define SRC_ADC_RVOL 0x6d
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#define SRC_TRUNC_N_OFF 0x00
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#define SRC_INT_REGS_OFF 0x01
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#define SRC_ACCUM_FRAC_OFF 0x02
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#define SRC_VFREQ_FRAC_OFF 0x03
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/* miscellaneous control defines */
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#define SRC_IOPOLL_COUNT 0x1000UL
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#define SRC_SYNTHFREEZE (1UL << 21)
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#define SRC_DACFREEZE (1UL << 20)
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#define SRC_ADCFREEZE (1UL << 19)
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static int src_reg_read(const DEV_STRUCT * DSP, u16_t reg, u16_t
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*data);
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static int src_reg_write(const DEV_STRUCT * DSP, u16_t reg, u16_t val);
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int src_init ( DEV_STRUCT * DSP ) {
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u32_t i;
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int retVal;
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/* Clear all SRC RAM then init - keep SRC disabled until done */
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/* Wait till SRC_RAM_BUSY is 0 */
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if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
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return (SRC_ERR_NOT_BUSY_TIMEOUT);
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pci_outl(reg(SAMPLE_RATE_CONV), SRC_DISABLE);
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/* from the opensound system driver, no idea where the specification is */
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/* there are indeed 7 bits for the addresses of the SRC */
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for( i = 0; i < 0x80; ++i ) {
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if (SRC_SUCCESS != (retVal = src_reg_write(DSP, (u16_t)i, 0U)))
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return (retVal);
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}
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_SYNTH_BASE + SRC_TRUNC_N_OFF, 16 << 4)))
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return (retVal);
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if (SRC_SUCCESS != (retVal = src_reg_write(DSP,
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SRC_SYNTH_BASE + SRC_INT_REGS_OFF, 16 << 10)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_DAC_BASE + SRC_TRUNC_N_OFF, 16 << 4)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_DAC_BASE + SRC_INT_REGS_OFF, 16 << 10)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_SYNTH_LVOL, 1 << 12)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_SYNTH_RVOL, 1 << 12)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_DAC_LVOL, 1 << 12)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_DAC_RVOL, 1 << 12)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_ADC_LVOL, 1 << 12)))
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return (retVal);
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if (SRC_SUCCESS != (retVal =
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src_reg_write(DSP, SRC_ADC_RVOL, 1 << 12)))
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return (retVal);
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/* default some rates */
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src_set_rate(DSP, SRC_SYNTH_BASE, SRC_RATE);
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src_set_rate(DSP, SRC_DAC_BASE, SRC_RATE);
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src_set_rate(DSP, SRC_ADC_BASE, SRC_RATE);
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/* now enable the whole deal */
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if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
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return (SRC_ERR_NOT_BUSY_TIMEOUT);
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pci_outl(reg(SAMPLE_RATE_CONV), 0UL);
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return 0;
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}
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static int src_reg_read(const DEV_STRUCT * DSP, u16_t reg, u16_t *data) {
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u32_t dtemp;
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/* wait for ready */
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if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
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return (SRC_ERR_NOT_BUSY_TIMEOUT);
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dtemp = pci_inl(reg(SAMPLE_RATE_CONV));
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/* assert a read request */
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/*pci_outl(reg(SAMPLE_RATE_CONV),
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(dtemp & SRC_CTLMASK) | ((u32_t) reg << 25));*/
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pci_outl(reg(SAMPLE_RATE_CONV), (dtemp &
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(DIS_REC|DIS_P2|DIS_P1|SRC_DISABLE)) | ((u32_t) reg << 25));
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/* now wait for the data */
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if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
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return (SRC_ERR_NOT_BUSY_TIMEOUT);
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if (NULL != data)
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*data = (u16_t) pci_inl(reg(SAMPLE_RATE_CONV));
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return 0;
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}
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static int src_reg_write(const DEV_STRUCT * DSP, u16_t reg, u16_t val) {
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u32_t dtemp;
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/* wait for ready */
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if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
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return (SRC_ERR_NOT_BUSY_TIMEOUT);
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dtemp = pci_inl(reg(SAMPLE_RATE_CONV));
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/* assert the write request */
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pci_outl(reg(SAMPLE_RATE_CONV),
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(dtemp & SRC_CTLMASK) | SRC_RAM_WE | ((u32_t) reg << 25) | val);
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return 0;
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}
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void src_set_rate(const DEV_STRUCT * DSP, char base, u16_t rate) {
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u32_t freq, dtemp, i;
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u16_t N, truncM, truncStart, wtemp;
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if( base != SRC_ADC_BASE )
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{
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/* freeze the channel */
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dtemp = base == SRC_SYNTH_BASE ? SRC_SYNTHFREEZE : SRC_DACFREEZE;
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for( i = 0; i < SRC_IOPOLL_COUNT; ++i )
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if( !(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_RAM_BUSY) )
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break;
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pci_outl(reg(SAMPLE_RATE_CONV),
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(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_CTLMASK) |
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dtemp);
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/* calculate new frequency and write it - preserve accum */
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/* please don't try to understand. */
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freq = ((u32_t) rate << 16) / 3000U;
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src_reg_read(DSP, base + SRC_INT_REGS_OFF, &wtemp);
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src_reg_write(DSP, base + SRC_INT_REGS_OFF,
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(wtemp & 0x00ffU) |
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((u16_t) (freq >> 6) & 0xfc00));
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src_reg_write(DSP, base + SRC_VFREQ_FRAC_OFF, (u16_t) freq >> 1);
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/* un-freeze the channel */
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dtemp = base == SRC_SYNTH_BASE ? SRC_SYNTHFREEZE : SRC_DACFREEZE;
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for( i = 0; i < SRC_IOPOLL_COUNT; ++i )
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if( !(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_RAM_BUSY) )
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break;
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pci_outl(reg(SAMPLE_RATE_CONV),
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(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_CTLMASK) &
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~dtemp);
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}
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else /* setting ADC rate */
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{
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/* freeze the channel */
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for( i = 0; i < SRC_IOPOLL_COUNT; ++i )
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if( !(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_RAM_BUSY) )
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break;
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pci_outl(reg(SAMPLE_RATE_CONV),
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(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_CTLMASK) |
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SRC_ADCFREEZE);
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/* derive oversample ratio */
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N = rate/3000U;
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if( N == 15 || N == 13 || N == 11 || N == 9 )
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--N;
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src_reg_write(DSP, SRC_ADC_LVOL, N << 8);
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src_reg_write(DSP, SRC_ADC_RVOL, N << 8);
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/* truncate the filter and write n/trunc_start */
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truncM = (21*N - 1) | 1;
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if( rate >= 24000U )
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{
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if( truncM > 239 )
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truncM = 239;
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truncStart = (239 - truncM) >> 1;
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src_reg_write(DSP, base + SRC_TRUNC_N_OFF,
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(truncStart << 9) | (N << 4));
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}
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else
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{
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if( truncM > 119 )
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truncM = 119;
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truncStart = (119 - truncM) >> 1;
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src_reg_write(DSP, base + SRC_TRUNC_N_OFF,
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0x8000U | (truncStart << 9) | (N << 4));
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}
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/* calculate new frequency and write it - preserve accum */
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freq = ((48000UL << 16) / rate) * N;
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src_reg_read(DSP, base + SRC_INT_REGS_OFF, &wtemp);
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src_reg_write(DSP, base + SRC_INT_REGS_OFF,
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(wtemp & 0x00ffU) |
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((u16_t) (freq >> 6) & 0xfc00));
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src_reg_write(DSP, base + SRC_VFREQ_FRAC_OFF, (u16_t) freq >> 1);
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/* un-freeze the channel */
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for( i = 0; i < SRC_IOPOLL_COUNT; ++i )
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if( !(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_RAM_BUSY) )
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break;
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pci_outl(reg(SAMPLE_RATE_CONV),
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(pci_inl(reg(SAMPLE_RATE_CONV)) & SRC_CTLMASK) &
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~SRC_ADCFREEZE);
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}
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return;
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}
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